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Functional Description
185
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
JTAG Interface
3.3
Functional Description
shows a high-level conceptual drawing of the JTAG module. The JTAG module is composed of
the TAP controller and serial shift chains with parallel update registers. The TAP controller is a simple
state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on
the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI toward TDO, and update the parallel load
registers. The current state of the TAP controller also determines whether the IR chain or one of the DR
chains is being accessed.
The serial shift chains with parallel load registers are comprised of one IR chain and multiple DR chains.
The current instruction loaded in the parallel load register determines which DR chain is captured, shifted,
or updated during the sequencing of the TAP controller.
Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift, or
update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to
ensure that the serial path between TDI and TDO is always connected (see
for a list of
implemented instructions).
Depending on the reset source, the effect on the JTAG module varies. The following reset sources reset
the entire JTAG module:
•
Externally generated power-on reset (POR)
The following reset sources reset only the JTAG pin configuration:
•
RST pin POR
•
Brownout POR
•
Watchdog POR
•
HIB module POR
•
RST pin system reset
•
Brownout system reset
•
Software system reset request (using the SYSRESREQ bit in the APINT register)
•
Software peripheral reset
•
Watchdog system reset
•
HIB module system reset
3.3.1 JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO.
lists these pins
and their associated state after a power-on reset or reset caused by the RST input. Detailed information
on each pin follows.
NOTE:
The following pins are configured as JTAG port pins out of reset. See
for
information on how to reprogram the configuration of these pins.
Table 3-1. JTAG Port Pins State After POR or RST Assertion
Pin Name
Data Direction
Internal Pullup
Internal Pulldown
Drive Strength
Drive Value
TCK
Input
Enabled
Disabled
N/A
N/A
TMS
Input
Enabled
Disabled
N/A
N/A
TDI
Input
Enabled
Disabled
N/A
N/A
TDO
Output
Enabled
Disabled
2-mA driver
Hi-Z