
ROM
FWBn
(32 word write
buffers)
CORTEX M4
2x256-bit
Prefetch Buffer 1
2x256-bit
Prefetch Buffer 0
ICODE
DCODE
SRAM
(four-way
interleaved banks)
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
FMC2
FWBVAL
FSIZE
FLASHPP
SSIZE
FLASHCONF
FLASHDMASZ
FLASHDMAST
Flash Control
Flash Write
Buffer Control
FMPREn
FMPPEn
Flash Protection
SRAM Control
Flash Array
(2-Way Interleaved)
BOOTCFG
USER_REGn
User Registers
Bus Matrix
ROMSWMAP
SCV
RVP
USRPWRUP
FLPEKEY
DMA
SPB
To Peripherals
Boot Registers
EESIZE
EEBLOCK
EEOFFSET
EERDWR
EEDWRINC
EEDONE
EESUPP
EEUNLOCK
EEPROT
EEPASSn
EEINT
EEHIDE
EEDBGME
EEPROMPP
EEPROM Control
EEPROM Array
DMA Control
SPB
8-KB Sectors
8-KB Sectors
8-KB Sectors
8-KB Sectors
Block Diagram
532
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
Internal Memory
7.1
Block Diagram
shows the internal memory and control structure. The dashed box in the figure indicate
registers residing in the System Control module.
Figure 7-1. Internal Memory Block Diagram
7.2
Functional Description
This section describes the functionality of the SRAM, ROM, flash, and EEPROM memories.
NOTE:
The µDMA has read-only access to flash (in run mode only).