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System Control Registers
256
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
System Control
4.2.23 DSLPPWRCFG Register (Offset = 0x18C) [reset = 0x0]
Deep-Sleep Power Configuration (DSLPPWRCFG)
This register provides configuration information for the power control of the SRAM and flash memory while
in deep-sleep mode.
DSLPPWRCFG is shown in
and described in
.
Return to
Figure 4-29. DSLPPWRCFG Register
31
30
29
28
27
26
25
24
RESERVED
R-0x0
23
22
21
20
19
18
17
16
RESERVED
R-0x0
15
14
13
12
11
10
9
8
RESERVED
LDOSM
TSPD
R-0x0
R/W-0x0
R/W-0x0
7
6
5
4
3
2
1
0
RESERVED
FLASHPM
RESERVED
SRAMPM
R-0x0
R/W-0x0
R-0x0
R/W-0x0
Table 4-35. DSLPPWRCFG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-10
RESERVED
R
0x0
9
LDOSM
R/W
0x0
LDO Sleep Mode
0x0 = LDO is disabled in sleep mode.
0x1 = LDO is placed in a low-power mode when deep-sleep mode is
entered.
8
TSPD
R/W
0x0
Temperature Sense Power Down.
This bit controls low-power mode for the internal temperature sensor
in the ADC.
0x0 = Temperature sensor in the ADC is disabled in sleep-mode.
0x1 = The internal temperature sensor in the ADC is placed in a low-
power mode when deep-sleep mode is entered.
7-6
RESERVED
R
0x0
5-4
FLASHPM
R/W
0x0
Flash Power Modes.
This field enables the flash to be placed in a low-power mode. See
the device-specific data sheet for information regarding wake times
from Sleep and deep sleep. If using the LFIOSC as the deep-sleep
clock source, FLASHPM = 0x2 must be used. If FLASHPM = 0x0
and the LFIOSC is used, current could be higher and could vary.
0x0 = Active Mode. Flash memory is not placed in a lower-power
mode. This mode provides the fastest time to sleep and wakeup but
the highest power consumption while the microcontroller is in deep-
sleep mode.
0x1 = Reserved
0x2 = Low-power mode. Flash memory is placed in low-power mode.
This mode provides the lowers power consumption but requires
more time to come out of deep-sleep mode.
0x3 = Reserved
3-2
RESERVED
R
0x0