Intel
®
Itanium
®
Architecture Software Developer’s Manual, Rev. 2.3
231
Processor Status Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:24
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:29
Control Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:30
Default Control Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:31
Page Table Address Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:35
Interruption Status Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:37
ITIR Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:39
Interruption Function State Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:41
Virtualized Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:44
Purge Behavior of TLB Inserts and Purges . . . . . . . . . . . . . . . . . . . . . . . . . 2:52
Purge behavior of VHPT Inserts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:53
Translation Interface Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:54
Page Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:56
Architected Page Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:58
Region Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:58
Protection Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:59
Translation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:60
VHPT Long-format Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:64
TLB and VHPT Search Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:70
Virtual Addressing Memory Attribute Encodings . . . . . . . . . . . . . . . . . . . . . . 2:76
Physical Addressing Memory Attribute Encodings . . . . . . . . . . . . . . . . . . . . . 2:77
Permitted Speculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:80
Register Return Values on Non-faulting Advanced/Speculative Loads . . . . . . . . . . . 2:80
Ordering Semantics and Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:83
Ordering Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:84
ALAT Behavior on Non-faulting Advanced/Check Loads . . . . . . . . . . . . . . . . . . 2:88
ISR Settings for Non-access Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 2:104
Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:105
Exception Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:106
Qualified Exception Deferral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:107
Spontaneous Deferral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:107
Interruption Vector Table (IVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:113
Interrupt Priorities, Enabling, and Masking . . . . . . . . . . . . . . . . . . . . . . . . . 2:119
External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:122
Task Priority Register Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:124
Interval Timer Vector Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:125
Performance Monitor Vector Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:126
Corrected Machine Check Vector Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 2:126
Local Redirection Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:127
Address Fields for Inter-processor Interrupt Messages . . . . . . . . . . . . . . . . . . . 2:129
Data Fields for Inter-processor Interrupt Messages . . . . . . . . . . . . . . . . . . . . . 2:129
RSE Internal State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:135
RSE Operation Instructions and State Modification . . . . . . . . . . . . . . . . . . . . . 2:138
RSE Modes (RSC.mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:139
Backing Store Pointer Application Registers . . . . . . . . . . . . . . . . . . . . . . . . 2:142
RSE Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:143
RSE Interruption Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:145
Debug Breakpoint Register Fields (DBR/IBR) . . . . . . . . . . . . . . . . . . . . . . . . 2:153
Debug Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:153
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...