Volume 2, Part 1: Addressing and Protection
2:67
the tag (ti bit) is zero for all valid tags. The hash index and tag together must uniquely
identify a translation. The processor must ensure that the indices into the hashed table,
the region’s preferred page size, and the tag specified in an indexed entry can be used
in a reverse hash function to uniquely regenerate the region identifier and virtual
address used to generate the index and tag. This must be possible for all supported
page sizes, implemented virtual addresses and legal values of region identifiers. A hash
function is reversible if using the hash result and all but one input produces the missing
input as the result of the reverse hash function. The easiest hash function and reverse
hash function is a simple XOR of bits. To ensure uniqueness, software must follow these
rules:
1. Software must use only one preferred page size for each unique region identifier
at any given time; otherwise, processor operation is undefined.
2. All tags for translations within a given region must be created with the preferred
page size assigned to the region; otherwise, processor operation is undefined.
3. Software is not allowed to have pages in the VHPT that are smaller than the
preferred page size for the region; otherwise, processor operation is undefined.
Software can specify a page with a page size larger than the preferred page size
in the VHPT, but tag values for the entries representing that page size must be
generated using the preferred page size assigned to that region.
4. To reuse a region identifier with a different preferred page size, software must
first ensure that the VHPT contains no insertable translations for that rid, purge
all translations for that rid from all processors that may have used it, and then
update the region register with the new preferred page size.
4.1.7
VHPT Environment
The processor’s VHPT walker can optionally be configured to search the VHPT for a
translation after a failed instruction or data TLB search. The VHPT walker is enabled for
different types of references under the following conditions:
• Data and non-access references (including IA-32): PTA.ve=1, and
RR[VA{63:61}].ve=1, and PSR.dt=1.
• Instruction fetches (including IA-32): PTA.ve=1, and RR[VA{63:61}].ve=1, and
PSR.dt=1, and PSR.it=1, and PSR.ic=1.
• RSE references: PTA.ve=1, and RR[VA{63:61}].ve=1, and PSR.dt=1, and
PSR.rt=1.
If the walker is not enabled, and an attempt is made to reference the VHPT, an
Alternate Instruction/Data TLB Miss fault is raised. The remainder of this section
assumes that the VHPT is enabled.
Region registers must support all implemented page sizes so software can use IHA,
thash
and
ttag
to manage the VHPT.
thash
and
ttag
are defined to operate on all
page sizes supported by the translation cache, regardless of the VHPT walker’s
supported page sizes. The PTA register must be implemented on processor models that
do not implement a VHPT walker. Software must ensure PTA is initialized and serialized
before issuing
ttag
,
thash
, before enabling the VHPT walker or issuing a reference that
may cause a VHPT walk. The minimum VHPT size is 32KBytes (PTA.size=15), and
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...