2:588
Volume 2, Part 2: Floating-point System Software
SWA Faults, is limited to the scalar reciprocal and scalar reciprocal square-root
approximation instructions and is not implementation dependent. It is required for the
correctness of the divide and square root algorithms.
8.1.1.1
SWA Faults
The Itanium architecture allows an implementation to raise SWA faults as required.
Therefore an implementation-independent operating system must be able to emulate
the architectural behavior of all FP instructions that can raise a floating-point exception.
However, hardware implementations will limit the cases that raise SWA Faults for
performance reasons. The most likely cases would be for the consumption of
denormalized or unnormalized operands and production of denormalized results.
The general flow of the SWA Fault handler is as follows:
1. From the interruption instruction bundle pointer (IIP) and faulting instruction
index (IPSR.ri), determine the FP instruction that faulted.
2. From the instruction, decode the opcode, static precision, status field and
input/output register specifiers.
3. Read the data from the input registers.
4. From the opcode and the FPSR’s status field, decode the result range and
precision.
5. From the ISR.code, determine that a SWA Fault has occurred, if not go to the last
step.
6. From the FPSR, determine if the trap disabled or trap enabled result is wanted.
7. Emulate the Itanium instruction to produce the Itanium architecture specified
result.
8. Place the result(s) in the correct FR and/or PR registers, if required.
9. Update the flags in the appropriate status field of the FPSR, if required.
10. Update the ISR.code if required. (This is required if the SWA fault has been
translated into an IEEE fault or trap.)
11. Check to see if an IEEE fault or trap needs to be raised. If so, then queue it to the
IEEE Filter, otherwise continue checking for lower priority traps that may need to
be raised and if required invoke their handler. When finished, continue execution
at the next instruction.
8.1.1.2
SWA Traps
SWA traps are allowed in the Itanium architecture as an optimization for cases when
the hardware implementation has produced the result of the first (exponent
unbounded) IEEE rounding
1
and can't continue with the second (exponent bounded)
IEEE rounding to produce the final result. One option for the implementation would be
to throw away the first IEEE rounding result and raise the SWA Fault. The SWA Fault
handler would then have to redo the computation of the first IEEE rounding. A
potentially more efficient option would be for the implementation to return the first
IEEE rounding result and raise a SWA trap. Returning the first IEEE rounded result is
1.
ANSI/IEEE Std 754-1985 sections 7.3 Overflow and 7.4 Underflow.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...