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Volume 2, Part 1: Processor Abstraction Layer
PAL_CACHE_READ
PAL_CACHE_READ – Read Values from the Processor Cache (259)
Purpose:
Reads the data and tag of a processor-controlled cache line for diagnostic testing.
Calling Conv:
Stacked Registers
Mode:
Physical
Buffer:
Not dependent
Arguments:
Returns:
Status:
Description:
A value is read from the specified cache line, if present. This procedure allows reading
cache data, tag, protection, or status bits.
The
line_id
argument is an 8-byte quantity in the following format:
•
cache_type
–
Unsigned 8-bit integer denoting whether to read from instruction (1)
or data/unified (2) cache. All other values are reserved.
•
level
–
Unsigned 8-bit integer specifying which cache within the cache hierarchy to
read. This value must be in the range from 0 up to one less than the
cache_levels
return value from PAL_CACHE_SUMMARY.
•
way
–
Unsigned 8-bit integer denoting within which cache way to read. If the cache
is direct-mapped this argument is ignored.
•
part
–
Unsigned 8-bit integer denoting which portion of the specified cache line to
read:
Argument
Description
index
Index of PAL_CACHE_READ within the list of PAL procedures.
line_id
8-byte formatted value describing where in the cache to read the data.
address
64-bit 8-byte aligned physical address from which to read the data. The address must be an
implemented physical address on the processor model with bit 63 set to zero.
Reserved
0
Return Value
Description
status
Return status of the PAL_CACHE_READ procedure.
data
Right-justified value returned from the cache line.
length
The number of bits returned in
data
.
mesi
The status of the cache line.
Status Value
Description
1
The word at
address
was found in the cache, but the line was invalid.
0
Call completed without error.
-1 Unimplemented
procedure
-2
Invalid argument
-3
Call completed with error.
-5
The word at
address
was not found in the cache.
-7
The operation requested is not supported for this
cache_type
and
level.
Figure 11-8. Layout of
line_id
Return Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
part
way
level
cache_type
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
reserved
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...