Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 154 / 1898

Volume 1, Part 2: Introduction to Programming for the Intel
®
Itanium
®
Architecture 1:143
This code assumes
r5
is ready when accessed and that there are sufficient instructions
to fill the latency between the
ld8.s
and the
chk.s
.
2.4.4 Data Speculation
Data speculation allows loads to be moved above possibly conflicting memory
references.
Advanced loads exclusively refer to data speculative loads. Review the
order of loads and stores in this assembly sequence:
st8 [r55]=r45 // Cycle 0
ld8 r3=[r5] ;; // Cycle 0
shr r7=r3,r87 // Cycle 2
The Itanium architecture allows the programmer to move the load above the store even
if it is not known whether the load and the store reference overlapping memory
locations. This is accomplished using special advanced load and check instructions:
ld8.a r3=[r5] // Advanced load
// Other instructions
st8 [r55]=r45 // Cycle 0
ld8.c r3=[r5] // Cycle 0 - check
shr r7=r3,r87 // Cycle 0
Note: The
shr
instruction in this schedule could issue in cycle 0 if there were no con-
flicts between the advanced load and intervening stores. If there were a con-
flict, the check load instruction (
ld8.c
) would detect the conflict and reissue
the load.
2.5 Predication
Predication is the conditional execution of an instruction based on a qualifying
predicate. A qualifying predicate is a predicate register whose value determines
whether the processor commits the results computed by an instruction.
The values of predicate registers are set by the results of instructions such as compare
(
cmp
) and test bit (
tbit
). When the value of a qualifying predicate associated with an
instruction is true (1), the processor executes the instruction, and instruction results
are committed. When the value is false (0), the processor discards any results and
raises no exceptions. Consider the following C code:
if (a) {
b = c + d;
}
if (e) {
h = i + j;
}