Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 539 / 1898

Volume 2, Part 1: Processor Abstraction Layer 2:291
• PSR: PSR.bn is 1; PSR.df1 and PSR.dfh are 1 if the floating-point unit failed self
test. All other PSR bits are 0. PSR.ic and PSR.i are zero to ensure external
interrupts, NMI and PMI interrupts are disabled.
• CRs: The contents of all control registers are undefined except the following:
• DCR: contains the value 0.
• IVA: contains the physical address of an interruption vector table previously
set up by PAL. SAL may choose to change this value. The IVA will be 0 when
the SALE_ENTRY State Parameter function is RECOVERY CHECK.
• RRs: The contents of all region registers are undefined.
• PKRs: The contents of all protection key registers are undefined.
• DBRs: The contents of all data breakpoint registers are undefined
• IBRs: The contents of all instruction breakpoint registers are undefined.
• PMCs: The contents of all performance monitor control registers are undefined.
• PMDs: The contents of all performance monitor data registers are undefined.
• Cache: The processor internal caches are enabled and invalidated. Unless directed
otherwise by the self-test control word, phase one of the processor self-test verifies
the caches themselves and the paths from the caches to the processor core. The
path from external memory to the caches cannot be tested until phase two of the
processor self-test.
Note: All cache contents will be invalidated when SAL returns to PAL after the
RECOVERY_CHECK hand-off. If the SAL uses the caches in their
RECOVERY_CHECK code, it is SAL's responsibility to write back any
modified data in the caches before returning to PAL
• TLB: The TRs and TCs are initialized with all entries having been invalidated. The
TLB is disabled because PSR.it=PSR.dt=PSR.rt=0. The TLBs cannot be fully tested
until phase two of the processor self-test.
Prior to passing control to SALE_ENTRY, PALE_RESET must ensure that the processor
Interrupt block pointer is set to point to address 0x0000_0000_FEE0_0000.
11.2.2.1 Definition of SALE_ENTRY State Parameter
• function
–
An 8-bit field indicating the reason for branching to SALE_ENTRY.
All other values of function are reserved.
Figure 11-7. SALE_ENTRY State Parameter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved status function
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
min-state_size reserved
Table 11-3. function Field Values
Function Value Description
RESET 0 System reset or power-on
MACHINE CHECK 1 Machine check event
INIT 2 Initialization event
RECOVERY CHECK 3 Check for recovery condition