Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 369 / 1898

Volume 2, Part 1: Interruptions 2:121
ssm PSR.i
;;
srlz.d // external interrupts may be sampled anywhere here
;;
rsm PSR.i
The stop following the
srlz.d
instruction in the above code sequence is required to
force the Reset System Mask (
rsm
) instruction into a subsequent instruction group. The
stop guarantees that the
srlz.d
will open the external interrupt window for at least one
cycle before the
rsm
instruction closes it again.
Note: In the above code sequence, the effect of disabling interrupts due to the
rsm
instruction is observed on the next instruction following the
rsm
.
5.8.2.3 Disabling of External Interrupt Delivery and rsm
When the current privilege level is zero, an
rsm
instruction whose mask includes PSR.i
may cause external interrupt delivery to be disabled for an implementation-dependent
number of instructions, even if the qualifying predicate for the
rsm
instruction is false.
Architecturally, the extents of this delivery disable “window” are defined as follows:
1. External interrupt delivery may be disabled for any instructions in the same
instruction group as the
rsm
, including those that precede the
rsm
in sequential
program order, regardless of the value of the qualifying predicate of the
rsm
instruction.
2. If the qualifying predicate of the
rsm
is true, then external interrupt delivery is
disabled immediately following the
rsm
instruction.
3. If the qualifying predicate of the
rsm
is false, then external interrupt delivery may
be disabled until the next data serialization operation that follows the
rsm
instruction.
The delivery disable window is guaranteed to be no larger than defined by the above
criteria, but it may be smaller, depending on the implementation.
When the current privilege level is non-zero, an
rsm
instruction whose mask includes
PSR.i may briefly disable external interrupt delivery, regardless of the value of the
qualifying predicate of the
rsm
instruction. However, the implementation guarantees
that non-privileged code cannot lock out external interrupts indefinitely (e.g., via an
arbitrarily long sequence of
rsm
PSR.i instructions with zero-valued qualifying
predicates).
5.8.3 External Interrupt Control Registers
Software interacts with external interrupts by reading and writing the external interrupt
control registers (CR64-81). These registers are summarized in
Table 5-9 , and are used
to prioritize and deliver external interrupts, and to assign external interrupt vectors for
processor-internal interrupt sources such as interval timer, performance monitoring,
and corrected machine check.
The external interrupt control registers can only be accessed at privilege level 0,
otherwise a Privileged Operation fault is raised.