Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 826 / 1898

2:578 Volume 2, Part 2: Memory Management
When one of the subdivided pages is referenced and does not have a translation in the
TLB, a TLB miss will occur. The handler for this fault can then use the faulting address
to calculate the appropriate offset into the sub-table and insert the corresponding
4KByte PTE into the TLB.
Some care is required to ensure forward progress for IA-32 instructions. Each IA-32
instruction can reference up to 8 distinct memory pages during its execution (see also
Section 10.6.3, “IA-32 TLB Forward Progress Requirements” ). This means that the fault
handler not only has to insert the PTE for the current fault into the TLB, but also the
PTEs for up to seven faults that occurred before, if these faults originate from the same
IA-32 instruction. This can be accomplished by maintaining a buffer for the most recent
faulting IIP and for the parameters of up to 7 TLB insertions. If a TLB fault occurs while
executing in IA-32 mode and the IIP matches the most recent IIP, all TLB insertions in
the buffer have to be repeated and the parameters for the new TLB fault must be added
to the buffer. Otherwise, the buffer can be cleared out and the most recent IIP can be
updated. The buffer also has to be cleared out when a TLB purge occurs.
§
Figure 5-2. Subpaging
Native Page Table
16K PTE
16K PTE
16K PTE
16K PTE
4K PTE
4K PTE
4K PTE
4K PTE
Sub-table
001 1