Volume 3: Pseudo-Code Functions
3:289
tlb_may_purge_itc_entries(rid, vaddr,
size)
May locally purge ITC entries that match the specified virtual address (
vaddr
), region
identifier (
rid
) and page size (
size
). May also invalidate entries that partially overlap
the parameters. The extent of purging is implementation dependent. If the purge size
is not supported, an implementation may generate a machine check abort or over
purge the translation cache up to and including removal of all entries from the
translation cache.
tlb_must_purge_dtc_entries(rid, vaddr,
size)
Purges all local, possibly overlapping, DTC entries matching the specified region
identifier (
rid
), virtual address (
vaddr
) and page size (
size)
.
vaddr{63:61}
(VRN) is ignored in the purge, i.e all entries that match
vaddr
{60:0} must be purged
regardless of the VRN bits. If the purge size is not supported, an implementation may
generate a machine check abort or over purge the translation cache up to and
including removal of all entries from the translation cache. If the specified purge
values overlap with an existing DTR translation, an implementation may generate a
machine check abort.
tlb_must_purge_dtr_entries(rid, vaddr,
size)
Purges all local, possibly overlapping, DTR entries matching the specified region
identifier (
rid
), virtual address (
vaddr
) and page size (
size)
.
vaddr{63:61}
(VRN) is ignored in the purge, i.e all entries that match
vaddr
{60:0} must be purged
regardless of the VRN bits. If the purge size is not supported, an implementation may
generate a machine check abort or over purge the translation cache up to and
including removal of all entries from the translation cache.
tlb_must_purge_itc_entries(rid, vaddr,
size)
Purges all local, possibly overlapping, ITC entry matching the specified region
identifier (
rid
), virtual address (
vaddr
) and page size (
size
).
vaddr
{63:61} (VRN) is
ignored in the purge, i.e all entries that match
vaddr
{60:0} must be purged
regardless of the VRN bits. If the purge size is not supported, an implementation may
generate a machine check abort or over purge the translation cache up to and
including removal of all entries from the translation cache. If the specified purge
values overlap with an existing ITR translation, an implementation may generate a
machine check abort.
tlb_must_purge_itr_entries(rid, vaddr,
size)
Purges all local, possibly overlapping, ITR entry matching the specified region
identifier (
rid
), virtual address (
vaddr
) and page size (
size
).
vaddr
{63:61} (VRN) is
ignored in the purge, i.e all entries that match
vaddr
{60:0} must be purged
regardless of the VRN bits. If the purge size is not supported, an implementation may
generate a machine check abort or over purge the translation cache up to and
including removal of all entries from the translation cache.
tlb_purge_translation_cache(loop)
Removes 1 to N translations from the local processor’s ITC and DTC. The number of
entries removed is implementation specific. The parameter
loop
is used to generate
an implementation-specific purge parameter.
tlb_replacement_algorithm(tlb)
Returns the next ITC or DTC slot number to replace. Replacement algorithms are
implementation specific.
tlb
specifies to perform the algorithm on the ITC or DTC.
tlb_search_pkr(key)
Searches for a valid protection key register with a matching protection
key
. The
search algorithm is implementation specific. Returns the PKR register slot number if
found, otherwise returns Not Found.
Table 3-1.
Pseudo-code Functions (Continued)
Function
Operation
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...