Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 286 / 1898

2:38 Volume 2, Part 1: System State and Programming Model
Figure 3-10 , all 64-bits of the IIP must be implemented regardless of the size of the
physical and virtual address space supported by the processor model (see
“Unimplemented Address Bits” on page 2:73 ). IIP also receives byte-aligned IA-32
instruction pointers. The IIP, IPSR and IFS are used to restore processor state on a
Return From Interruption instruction (
rfi
). See “Interruption Vector Descriptions” on
page 2:165 for usages of the IIP.
An
rfi
to Itanium architecture-based code (IPSR.is is 0) ignores IIP{3:0}, an
rfi
to
IA-32 code (IPSR.is is 1) ignores IIP{63:32}. Ignored bits are assumed to be zero.
Control transfers to unimplemented addresses (see “Unimplemented Address Bits” on
page 2:73 ) result in an Unimplemented Instruction Address trap or fault. When the trap
or fault is delivered, IIP is written as follows:
• If the trap is taken for an unimplemented virtual address, IIP is written in one of
two ways, depending on the implementation: 1) IIP may be written with the
implemented virtual address bits IP{63:61} and IP{IMPL_VA_MSB:0} only. Bits
IIP{60:IMPL1} are set to IP{IMPL_VA_MSB}, i.e., sign-extended. 2) IIP
may be written with the full, unimplemented virtual address from IP.
• If the trap is taken for an unimplemented physical address, IIP is written in one of
two ways, depending on the implementation: 1) IIP may be written with the
physical addressing memory attribute bit IP{63} and the implemented physical
address bits IP{IMPL_PA_MSB:0} only. Bits IIP{62:IMPL1} are set to 0.
2) IIP may be written with the full, unimplemented physical address from IP.
When an
rfi
is executed with an unimplemented address in IIP (an unimplemented
virtual address if IPSR.it is 1, or an unimplemented physical address if IPSR.it is 0), and
an Unimplemented Instruction Address trap is taken, an implementation may optionally
leave IIP unchanged (preserving the unimplemented address in IIP).
Note: Since IP{3:0} are always 0 when executing Itanium architecture-based code,
IIP{3:0} will always be 0 when any interruption is taken from Itanium architec-
ture-based code, with the exception of an Unimplemented Instruction Address
trap on an
rfi
, where IIP may optionally be preserved as whatever value it
held before executing the
rfi
.
3.3.5.4 Interruption Faulting Address (IFA – CR20)
On an interruption and if PSR.ic is 1, the IFA receives the virtual address (or physical
address if translations are disabled) that raised a fault. IFA reports the faulting address
for both instruction and data memory accesses (including IA-32). For faulting data
references (including IA-32), IFA points to the first byte of the faulting data memory
operand. IFA reports a byte granular address. For faulting instruction references
(including IA-32), IFA contains the 16-byte aligned bundle address (IFA{3:0} are zero)
of the faulting instruction. For faulting IA-32 instructions, IIP points to the first byte of
the IA-32 instruction, and is byte granular. In the event of an IA-32 instruction
spanning a virtual page boundary, IA-32 instruction fetch faults are reported as either
(1) for faults on the first page, IFA is set to the bundle address (IFA{3:0}=0) of the
Figure 3-10. Interruption Instruction Bundle Pointer (IIP – CR19)
63 0
IIP
64