2:346
Volume 2, Part 1: Processor Abstraction Layer
When this optimization is enabled, execution of
rsm
and
ssm
instructions, with
PSR.vm==1 and system mask equal to zero (0x0), will not intercept to the VMM unless
a fault condition is detected (see
for details).
When PSR.vm==1, execution of
rsm
and
ssm
instructions
, which modify any bits other
than vpsr.ic and user mask fields will result in virtualization intercepts independent of
whether this optimization is enabled or not.
Synchronization is required when this optimization is enabled; see
details.
This optimization is not supported on all processor implementations. Software can call
PAL_VP_ENV_INFO to determine the availability of this feature.
When this optimization is enabled, certain VPD state is accessed, as described in
Table 11-16, “Virtual Processor Descriptor (VPD)” on page 2:326
.
11.7.4.3
Virtualization Disables
summarizes the virtualization disables supported in Itanium architecture.
1.
The execution of
rsm
and
ssm
instructions with PSR.vm==1 is affected by both the virtual external
interrupt optimization (a_int) and the interruption collection and user mask optimization (a_ic_um).
Software can enable or disable both optimizations together, or enable each optimization indepen-
dently.
Section 11.7.4.4.1, “Virtual External Interrupt Optimization and Interruption Collection and
User Mask Optimization” on page 2:349
describes the behavior when both optimizations are
enabled.
Table 11-44.Synchronization Requirements for Interrupt Collection and User
Mask Optimization
VPD Resource
Synchronization Required
vpsr.ic
Read, Write
Table 11-45.Interruptions when Interrupt Collection and User Mask
Optimization is Enabled
Instructions
Interruptions
rsm
,
ssm
When the interruption collection and user mask optimization is
enabled, execution of
rsm
and
ssm
instructions with PSR.vm==1
which modify vpsr.ic and any user mask fields, may raise the follow-
ing faults:
•Privileged Operation fault – if vpsr.cpl is not zero
Table 11-46. Virtualization Disables Summary
Disable
Virtualization
Disable Control
(
vdc
)
a
Description
Disable VMSW Instruction
d_vmsw
Disable External Interrupt Control Register Virtualization
d_extint
Disable Breakpoint Register Virtualization
d_ibr_dbr
Disable PMC Virtualization
d_pmc
Disable MOV-to-PMD Virtualization
d_to_pmd
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...