Volume 2, Part 1: Processor Abstraction Layer
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PAL_PTCE_INFO
PAL_PTCE_INFO – Get PTCE Purge Loop Information (6)
Purpose:
Returns information required for the architected loop used to purge (initialize) the
entire TC.
Calling Conv:
Static Registers Only
Mode:
Physical and Virtual
Buffer:
Not dependent
Arguments:
Returns:
Status:
Description:
No explicit hardware support is required by this call. See the purge loop example in the
description of the
ptc.e
instruction in
Chapter 2, “Instruction Reference” in Volume 3
.
Argument
Description
index
Index of PAL_PTCE_INFO within the list of PAL procedures.
Reserved
0
Reserved
0
Reserved
0
Return Value
Description
status
Return status of the PAL_PTCE_INFO procedure.
tc_base
Unsigned 64-bit integer denoting the beginning address to be used by the first PTCE
instruction in the purge loop.
tc_counts
Two unsigned 32-bit integers denoting the loop counts of the outer (loop 1) and inner (loop 2)
purge loops. count1 (loop 1) is contained in bits 63:32 of the parameter, and count2 (loop 2)
is contained in bits 31:0 of the parameter.
tc_strides
Two unsigned 32-bit integers denoting the loop strides of the outer (loop 1) and inner (loop 2)
purge loops. stride1 (loop 1) is contained in bits 63:32 of the parameter, and stride2 (loop 2)
is contained in bits 31:0 of the parameter.
Status Value
Description
0
Call completed without error
-2
Invalid argument
-3
Call completed with error
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...