Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 281 / 1898

Volume 2, Part 1: System State and Programming Model 2:33
A sequence of reads of the ITC is guaranteed to return ever-increasing values (except
for the case of the counter wrapping back to 0) corresponding to the program order of
the reads. Applications can directly sample the ITC for time-based calculations.
A 64-bit overflow condition can occur without notification. The ITC can be read at any
privilege level if PSR.si is zero. The timer can be secured from non-privileged access by
setting PSR.si to one. When secured, a read of the ITC by non-privileged code results in
a Privileged Register fault. Writes to the ITC can only be performed at privilege level 0;
otherwise, a Privileged Register fault is raised.
The IA-32 Time Stamp Counter (TSC) is similar to ITC. The ITC can be read by the
IA-32
rdtsc
(read time stamp counter) instruction. System software can secure the ITC
from non-privileged IA-32 access by setting either PSR.si or CFLG.tsd to 1. When
secured, an IA-32 read of the ITC at any privilege level other than the most privileged
raises an IA_32_Exception(GPfault).
When the value in the ITC is equal to the value in the ITM an Interval Timer Interrupt is
raised. Once the interruption is taken by the processor and serviced by software, the
ITC may not necessarily be equal to the ITM. The ITM is accessible only at privilege
level 0; otherwise, a Privileged Operation fault is raised.
The interval counter can be written, for initialization purposes, by privileged code. The
ITC is not architecturally guaranteed to be synchronized with any other processor’s
interval time counter in an multiprocessor system, nor is it synchronized with the wall
clock. Software must calibrate interval timer ticks to wall clock time and periodically
adjust for drift. In a multiprocessor system, a processor's ITC is not architecturally
guaranteed to be clocked synchronously with the ITC's on other processors, and may
not be clocked at the same nominal clock rate as ITC's on other processors. The
platform firmware provides information on the clocking of processors in a
multiprocessor system.
Modification of the ITC or ITM is not necessarily serialized with respect to instruction
execution. Software can issue a data serialization operation to ensure the ITC or ITM
updates and possible side effects are observed by a given point in program execution.
Software must accept a level of sampling error when reading the interval timer due to
various machine stall conditions, interruptions, bus contention effects, etc. Please see
the processor-specific documentation for further information on the level of sampling
error of the Itanium processor.
3.3.4.3 Resource Utilization Counter (RUC – AR45)
The Resource Utilization Counter (RUC) is a 64-bit counter that counts up at a fixed
relationship to the input clock to the processor, when the processor is active. Processors
may be inactive due to hardware multi-threading. Virtual processors may be inactive
when not scheduled to run by the VMM. (See
Section 11.7, “PAL Virtualization Support”
on page 2:324 for details on virtual processors.)
The RUC is clocked such that, in a given time interval, the difference in the RUC values
for all of the logical or virtual processors on a given physical processor add up to
approximately the difference seen in the ITC on that physical processor for that same
interval.