Volume 2, Part 2: Firmware Overview
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When an uncorrected machine check event occurs, SAL will invoke the OS_MCA
handler. The functionality of this handler is dependent on the OS. At a minimum, it
must call a SAL procedure to retrieve the error logging and state information and then
call another SAL procedure to release these resources for future error logging and state
save.
When the OS_MCA code completes, it decides whether or not to return to the
interrupted context. The OS must take into account the state information retrieved
from the SAL with respect to the continuability of the processor and system. Thus, even
if the OS could correct the error, if PAL or SAL reports that it did not capture the entire
processor context, resumption of the interrupted context will not be possible.
The OS must also determine from values stored by PAL in the min-state save area
whether the machine check occurred while operating with PSR.ic set to 0 and whether
the processor supports recovery for this case. Please refer to
“Resources Required for Machine Check and Initialization Event Recovery”
for more
information on processor recovery under this condition.
To provide better software error handling, some operating systems build mechanisms
to identify whether machine checks occurred during execution of the OS kernel code or
in the application context. One technique to achieve this is to call the PAL_MC_DRAIN
procedure when an application makes a system call to the OS. This procedure
completes all outstanding transactions within the processor and reports any pending
machine checks. This technique impacts system call and interrupt handling
performance significantly, but will improve system reliability by allowing the OS to
recover from more errors than if this mechanism was not included.
13.3.2
INIT Flows
INIT is an initialization event generated by the platform or by software through an
inter-processor interrupt message. The INIT can be due to a platform INIT event or due
to a failed rendezvous on an application processor.
The INIT event will pass control to the PAL firmware INIT handler. The PAL INIT handler
saves processor state to the registered min-state save area and sets up the architected
hand off state before branching to SAL. See
Section 11.5, “Platform Management
for more information on the PAL INIT handling.
The SAL INIT handler logs processor state and platform state information and then calls
the OS_INIT handler if one is registered. The OS_INIT handler gains control in physical
mode but may switch to virtual mode if necessary. The OS may choose to implement a
crash dump or an interactive debugger within the OS_INIT handler.
The OS must register the OS_INIT entry point with SAL, otherwise the occurrence of an
INIT event will cause a system reset. At the end of OS_INIT handling, the OS must
return to SAL with the appropriate exit status.
illustrates the flow of control during INIT processing.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...