Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 946 / 1898

Volume 3: Instruction Reference 3:47
cmpxchg
affect program functionality and may be ignored by the implementation. See
Section 4.4.6, “Memory Hierarchy Control and Consistency” on page 1:69 for details.
For
cmp8xchg16
, Illegal Operation fault is raised on processor models that do not
support the instruction. CPUID register 4 indicates the presence of the feature on the
processor model. See
Section 3.1.11, “Processor Identification Registers” on page 1:34
for details.
Operation: if (PR[ qp ]) {
size = sixteen_byte_form ? 16 : sz ;
if (sixteen_byte_form && !instruction_implemented(CMP8XCHG16))
illegal_operation_fault();
check_target_register( r
1
);
if (GR[ r
3
].nat || GR[ r
2
].nat)
register_nat_consumption_fault(SEMAPHORE);
paddr = tlb_translate(GR[ r
3
], size, SEMAPHORE, PSR.cpl, &mattr,
&tmp_unused);
if (!ma_supports_semaphores(mattr))
unsupported_data_reference_fault(SEMAPHORE, GR[ r
3
]);
if (sixteen_byte_form) {
if ( sem == ‘acq’)
val = mem_xchg16_cond(AR[CCV], GR[ r
2
], AR[CSD], paddr, UM.be,
mattr, ACQUIRE, ldhint );
else // ‘rel’
val = mem_xchg16_cond(AR[CCV], GR[ r
2
], AR[CSD], paddr, UM.be,
mattr, RELEASE, ldhint );
} else {
if ( sem == ‘acq’)
val = mem_xchg_cond(AR[CCV], GR[ r
2
], paddr, size, UM.be, mattr,
ACQUIRE, ldhint );
else // ‘rel’
val = mem_xchg_cond(AR[CCV], GR[ r
2
], paddr, size, UM.be, mattr,
RELEASE, ldhint );
val = zero_ext(val, size * 8);
}
if (AR[CCV] == val)
alat_inval_multiple_entries(paddr, size);
GR[ r
1
] = val;
GR[ r
1
].nat = 0;
}
Interruptions:
Illegal Operation fault Data Key Miss fault
Register NaT Consumption fault Data Key Permission fault
Unimplemented Data Address fault Data Access Rights fault
Data Nested TLB fault Data Dirty Bit fault
Alternate Data TLB fault Data Access Bit fault
VHPT Data fault Data Debug fault
Data TLB fault Unaligned Data Reference fault
Data Page Not Present fault Unsupported Data Reference fault
Data NaT Page Consumption fault