Volume 2, Part 1: Processor Abstraction Layer
2:463
PAL_TEST_PROC
•
test_phase
defines which phase of the processor self-tests are requested to be run.
A value of zero indicates to run phase two of the processor self-tests. Phase two of
the processor self-tests are ones that require external memory to execute correctly.
A value of one indicates to run phase one of the processor self-tests. Phase one of
the processor self-tests are tests run during PALE_RESET and do not depend on
external memory to run correctly. When the caller requests to have phase one of
the processor self-test run via this procedure call, a memory buffer may be needed
to save and restore state as required by the PAL calling conventions. The procedure
PAL_TEST_INFO informs the caller about the requirements of the memory buffer.
The
test_params
input argument specifies which memory attributes are allowed to be
used with the memory buffer passed to this procedure as well as the self-test control
word. The self-test control word
test_control
controls the runtime and coverage of the
processor self-test phase specified in the
test_phase
parameter.
•
attributes
specifies the memory attributes that are allowed to be used with the
memory buffer passed to this procedure. The
attributes
parameter is a vector
where each bit represents one of the virtual memory attributes defined by the
architecture. The bit field position corresponds to the numeric memory attribute
encoding defined in
Section 4.4, “Memory Attributes” on page 2:75
. The caller is
required to support the cacheable attribute for the memory buffer, otherwise an
invalid argument will be returned.
•
test_control
is the self-test control word corresponding to the
test_phase
passed.
This
test_control
directs the coverage and runtime of the processor self-tests
specified by the
test_phase
input argument. Information about the self-test control
word can be found in
Section 11.2.3, “PAL Self-test Control Word” on page 2:295
and information on if this feature is implemented and the number of bits supported
can be obtained by the PAL_TEST_INFO procedure call. If this feature is
implemented by the processor, the caller can selectively skip parts of the processor
self-test by setting
test_control
bits to a one. If a bit has a zero, this test will be
run. The values in the unimplemented bits are ignored. If PAL_TEST_INFO indicated
that the self-test control word is not implemented, this procedure will return with
an invalid argument status if the caller sets any of the
test_control
bits.
PAL_TEST_PROC will classify the processor after the self-test in one of four states:
CATASTROPHIC FAILURE, FUNCTIONALLY RESTRICTED, PERFORMANCE RESTRICTED,
or HEALTHY. These processor self-test states are described in
. If PAL_TEST_PROC returns in the FUNCTIONALLY RESTRICTED or
PERFORMANCE RESTRICTED states the
self-test_status
return value can provide
additional information regarding the nature of the failure. In the case of a
CATASTROPHIC FAILURE, the procedure does not return.
The procedure will only perform memory accesses to the buffer passed to it using the
memory attributes indicated in the
attributes
bit-field. The caller must ensure that the
memory region passed to the procedure is in a coherent state.
PAL_TEST_PROC may modify PSR bits or system registers as necessary to test the
processor. These bits or registers must be restored upon exit from PAL_TEST_PROC
Figure 11-45. Layout of
test_param
Argument
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
test_control
reserved
attributes
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
test_control
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
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Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...