Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 501 / 1898

Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications 2:253
10.4.1 Entering IA-32 Processes
High FP registers (FR32-127)
–
The processor requires access to all high FP registers
during the execution of IA-32 instructions. It is recommended on entering an IA-32
process, that the OS save the high FP registers belonging to a prior context and then
enable the high FP registers (PSR.dfh is 0). Otherwise, the processor will immediately
raise a Disabled FP Register fault on the first IA-32 instruction executed in the IA-32
process. Performing the state save of the prior high FP register context during the
context switch avoids the unnecessary generation of the Disabled FP Register fault.
Low FP registers (FR2-31)
–
The processor does not require access to the low FP
registers unless executing IA-32 FP, MMX technology or SSE instructions. It is
recommended on entry to an IA-32 process, that the OS
disable the low FP registers
by setting PSR.dfl to 1. PSR.dfl set to 0 indicates that there was a possibility that IA-32
FP, MMX technology or SSE instruction could execute and write FR8-31. If the low FP
registers are enabled on entry to an IA-32 process (PSR.dfl is 0), all low FP registers
will appear to be dirty on IA-32 process exit.
High Integer Registers (GR32-127)
–
Since the processor leaves all high registers in the
register stack in an undefined state, these registers must be saved by the RSE before
entering an IA-32 process.
Low Integer registers (GR1-31)
–
These registers must be explicitly saved before
entering an IA-32 process.
10.4.2 Exiting IA-32 Processes
High FP registers (FR32-127)
–
PSR.mfh is unmodified when leaving the IA-32
instruction set. IA-32 instruction set execution leaves FR32-127 in an undefined state.
Software can not rely on register values being preserved across an instruction set
transition. These registers do NOT need to be preserved across a context switch.
Low FP registers (FR2-31)
–
PSR.mfl indicates there is a possibility that FR8-31 were
modified by IA-32 FP, MMX technology, or SSE instruction. The modify bit is set by the
processor when leaving the IA-32 instruction set, if PSR.dfl is 0, otherwise PSR.mfl is
unmodified. During the state save of the outbound IA-32 process, it is recommended
that the OS save FR2-31 if and only if the lower FP registers are marked as modified.
High Integer Registers (GR32-127)
–
Since the processor leaves all high registers
undefined across an instruction set transition, these registers do NOT need to be
preserved across an IA-32 context switch.
Low Integer registers (GR1-31)
–
These registers must be explicitly preserved across a
context switch.
10.5 IA-32 Instruction Set Behavior Summary
Table 10-5 summarizes IA-32 instruction behavior within the Itanium System
Environment. All IA-32 instructions are unchanged from the Intel
®
64 and IA-32
Architectures Software Developer’s Manual except where noted. IA-32 instructions
can also generate additional Itanium register and memory faults as defined in