Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 782 / 1898

2:534 Volume 2, Part 2: MP Coherence and Synchronization
The release store ensures that the code image updates are made visible to the remote
processors in the proper order (i.e.
new_code
is updated before the branch at address
x
is updated). Using the final three instructions ensures that the remote processors will
see the new code the next time they execute the branch at address
x
.
On the local processor, the branch at address
x
also serves to force the pipeline to be
coherent with the code image update the machine without requiring an interrupt,
rfi
instruction, or
srlz.i
instruction. Table 2-16 enumerates the potential pipeline
behaviors to illustrate this point.
In the first and fourth scenarios, the pipeline fetches and executes either the old branch
and old target instruction or the new branch and new target instruction. Note that if the
pipeline sees the new branch, it must also see the new target instruction by virtue of
the way the code in
Figure 2-9 is written. Either of these behaviors is consistent.
In the second and third scenarios, the pipeline obtains a mix of the old or new branch
and the old or new target instruction. In these cases, the pipeline must flush because
the predicted target will not agree with the branch instruction.
This behavior is not guaranteed unless the branch at address
x
is IP-relative and taken.
The branch must be IP-relative to ensure that both the instruction and target address
can be atomically updated (this is only possible with an IP-relative branch because in
this type of branch, the target address is part of the instruction).
2.5.3 Programmed I/O
Programmed I/O requires that the CPU copy data from the device controller to main
memory using load instructions to read from the device and store instructions to write
data into cacheable memory (page-in).
To ensure correct operation, Itanium architecture-based software must exercise care in
the presence of Programmed I/O due to two features of the architecture. First, the
Itanium architecture does not require an implementation to maintain coherency
between local instruction and data caches for Itanium architecture-based code. Second,
the Itanium architecture allows aggressive instruction prefetching. Specifically, an
implementation can move any location from a cacheable page into its instruction
cache(s) any time a translation for the location indicates that the page is present (i.e.
the
p
bit of the translation is set).
A system that performs Programmed I/O can use a sequence similar to that shown in
Figure 2-8 to perform the data movement. Figure 2-10 presents a code sequence that
updates a code image on both the local and remote processors.
Table 2-16. Potential Pipeline Behaviors of the Branch at x from Figure 2-9
Pipeline Operation Scenario #1 Scenario #2 Scenario #3 Scenario #4
Fetch branch at
x
Old branch Old branch New branch New branch
Predict branch at
x
Old target New target Old target New target
Code at target Old instruction “New” instruction
(but could be stale)
Old instruction New instruction
Retire branch at
x
Old retires Must flush due to
misprediction
Must flush due
to misprediction
New retires