Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 386 / 1898

2:138 Volume 2, Part 1: Register Stack Engine
place at lower addresses, defined relative to BSP by the sizes of the clean and dirty
partitions. Although the stack is conceptually infinite in both directions, the effective
base of the stack is expected to be the first memory location of the first page allocated
to the backing store.
To allow the highest possible degree of concurrent execution, the processor and the
RSE operate independently of each other during normal program execution. The RSE
distinguishes between
mandatory and eager load/store operations. Mandatory
load/store operations occur as the result of
alloc
,
flushrs
,
loadrs
,
br.ret
or
rfi
instructions. Eager operations occur when the RSE is speculatively working ahead of
program execution, and it is not known whether this register spill/fill is actually
required by the program.
When the RSE works in the background, it issues eager RSE spill and fill operations to
extend the size of the clean partition in both directions—by decreasing the RSE load
pointer and loading values from the backing store into invalid registers (eager RSE
load), and by saving dirty registers to the backing store and increasing the RSE store
pointer (eager RSE store). Allocation of a sufficiently large frame (using
alloc
) or
execution of a
flushrs
instruction may cause the RSE to suspend program execution
and issue mandatory RSE stores until the required number of registers have been
spilled to the backing store. Similarly a
br.ret
or
rfi
back to a sufficiently large frame
or execution of a
loadrs
instruction may cause the RSE to suspend program execution
and issue mandatory RSE loads until the required number of registers have been
restored from the backing store. The RSE only operates in the foreground and suspends
program execution whenever forward progress of the program actually requires
registers to be spilled or filled.
Table 6-2 describes the RSE operation instructions and state modifications.
Table 6-2. RSE Operation Instructions and State Modification
Affected State
Instruction
alloc
r
1
= ar.pfs, i,l,
o,r
a
a. These instructions have undefined behavior with an incomplete frame. See “RSE Behavior with an Incomplete Register Frame”
on page 2:146.
br.call
a
, brl.call
a
br.ret
a
rfi
when CR[IFS].v = 1
AR[BSP]{63:3} unchanged AR[BSP]{63:3} + CFM.sol +
(AR[BSP]{8:3} + CFM.sol)/63 AR[BSP]{63:3} -
AR[PFS].pfm.sol -
(62-AR[BSP]{8:3}+
AR[PFS].pfm.sol)/63 AR[BSP]{63:3} -
CR[IFS].ifm.sof -
(62-AR[BSP]{8:3}+
CR[IFS].ifm.sof)/63
AR[PFS] unchanged AR[PFS].pfm = CFM
AR[PFS].pec = AR[EC]
AR[PFS].ppl = PSR.cpl unchanged unchanged
GR[
r
1
] AR[PFS] N/A N/A N/A
CFM CFM.sof =
i+l+o
CFM.sol =
i+l
CFM.sor =
r
>> 3
CFM.sof -= CFM.sol
CFM.sol = 0
CFM.sor = 0
CFM.rrb.gr = 0
CFM.rrb.fr = 0
CFM.rrb.pr = 0 AR[PFS].pfm
or
b
CFM.sof = 0
CFM.sol = 0
CFM.sor = 0
CFM.rrb.gr = 0
CFM.rrb.fr = 0
CFM.rrb.pr = 0
b. Normal
br.ret
instructions restore CFM with AR[PFS].pfm. However, if a bad PFS value is read by the
br.ret
instruction, all
CFM fields are set to zero. See “Bad PFS used by Branch Return” on page 2:143.
CR[IFS].ifm