Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 764 / 1898

2:516 Volume 2, Part 2: MP Coherence and Synchronization
2.2.1.7 Data Dependency Establishes Local Ordering
In the Itanium architecture, a dependency (e.g., a later operation reading the value
written by an earlier operation) can imply a local ordering relationship between the two
operations. This section focuses on dependencies through registers only.
Section 2.2.1.6 discusses dependencies and MP ordering.
The execution shown in Table 2-6 illustrates how data dependency and memory
ordering interact in a simple “pointer chase.”
In this example, Processor #0 could be executing code that updates a shared object
with M1 and then publishes a pointer to the object with M2. Processor #1 then loads
the pointer and dereferences it to read the contents of the shared object. The outcome
r1 = x and r2 = 0 implies that Processor #1 observes the new value of the object
pointer, y, but the old value of the data field, x.
The ordering semantics require but place no requirements on the relative
ordering of M3 and M4.
Thus, the memory semantics alone would allow the outcome r1 = x and r2 = 0 in the
absence of other constraints. Using an acquire load for M3 can avoid this outcome as
doing so forces
and thus prevents the outcome. However, this use of acquire
is non-intuitive given the RAW dependency through register r1 between M3 and M4.
That is, M3 produces a value that M4 requires in order to execute so how should it be
possible for them to go out of order? Further, using an acquire in this case prevents any
memory operation following M3 from moving above M3, even if they are completely
independent of M3.
To avoid this potential confusion and performance issue, the Itanium architecture treats
data dependency and memory ordering in the same fashion on the local processor. That
is, if
and A produces a value that B consumes, then on the local processor.
This relationship is also transitive as the execution in Table 2-7 illustrates.
The Processor #0 code is the same as in Table 2-6 . The Processor #1 now performs the
following operation: if the pointer value y is equal to x, load a value from x.
Table 2-6. Memory Ordering and Data Dependency
Processor #0 Processor #1
st [x] = 1 // M1
st.rel [y] = x // M2
ld r1 = [y] ;; // M3
ld r2 = [r1] // M4
Outcome: r1 = x and r2 = 0 is not allowed
Table 2-7. Memory Ordering and Data Dependency Through a Predicate
Register
Processor #0 Processor #1
st [x] = 1 // M1
st.rel [y] = x // M2
ld r1 = [y] // M3
cmp.eq p1, p2 = r1, x ;; // C1
(p1)ld r2 = [x] // M4
Outcome: r1 = x and r2 = 0 is not allowed
M1 M2

M3 M4

A B » A B
