Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 47 / 1898

1:36 Volume 1, Part 1: Execution Environment
3.2 Memory
This section describes an Itanium architecture-based application program’s view of
memory. This includes a description of how memory is accessed, for both 32-bit and
64-bit applications. The size and alignment of addressable units in memory is also
given, along with a description of how byte ordering is handled.
The system view of memory and of virtual memory management is given in Chapter 4,
“Addressing and Protection” in Volume 2 . The IA-32 instruction set view of memory
and virtual memory management is defined in Section 10.6, “System Memory Model”
on page 2:259 .
3.2.1 Application Memory Addressing Model
Memory is byte addressable and is accessed with 64-bit pointers. A 32-bit pointer
model without a hardware mode is supported architecturally. Pointers which are 32 bits
in memory are loaded and manipulated in 64-bit registers. Software must explicitly
convert 32-bit pointers into 64-bit pointers before use. For details on 32-bit addressing,
refer to
“32-bit Virtual Addressing” on page 2:71 .
3.2.2 Addressable Units and Alignment
Memory can be addressed in units of 1, 2, 4, 8, 10 and 16 bytes.
It is recommended that all addressable units be stored on their naturally aligned
boundaries. Hardware and/or operating system software may have support for
unaligned accesses, possibly with some performance cost. 10-byte floating-point values
should be stored on 16-byte aligned boundaries.
Bits within larger units are always numbered from 0 starting with the least-significant
bit. Quantities loaded from memory to general registers are always placed in the
least-significant portion of the register (loaded values are placed right justified in the
target general register).
Instruction bundles (three instructions per bundle) are 16-byte units that are always
aligned on 16-byte boundaries.
3.2.3 Byte Ordering
The UM.be bit in the User Mask controls whether loads and stores use little-endian or
big-endian byte ordering for Itanium architecture-based code. When the UM.be bit is 0,
larger-than-byte loads and stores are little endian (lower-addressed bytes in memory
correspond to the lower-order bytes in the register). When the UM.be bit is 1,
x2 33 Processor implements
mpy4
and
mpyshl4
instructions (see “tf — Test Feature”
instruction in Volume 3 ).
rv 63:34 Reserved.
Table 3-8. CPUID Register 4 Fields (Continued)
Field Bits Description