4:274
Volume 4: Base IA-32 Instruction Reference
LODS/LODSB/LODSW/LODSD—Load String Operand
Description
Load a byte, word, or doubleword from the source operand into the AL, AX, or EAX
register, respectively. The source operand is a memory location at the address DS:ESI.
(When the operand-size attribute is 16, the SI register is used as the source-index
register.) The DS segment may be overridden with a segment override prefix.
The LODSB, LODSW, and LODSD mnemonics are synonyms of the byte, word, and
doubleword versions of the LODS instructions. (For the LODS instruction, “DS:ESI”
must be explicitly specified in the instruction.)
After the byte, word, or doubleword is transfer from the memory location into the AL,
AX, or EAX register, the ESI register is incremented or decremented automatically
according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the
ESI register is incremented; if the DF flag is 1, the ESI register is decremented.) The
ESI register is incremented or decremented by 1 for byte operations, by 2 for word
operations, or by 4 for doubleword operations.
The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix
for block loads of ECX bytes, words, or doublewords. More often, however, these
instructions are used within a LOOP construct, because further processing of the data
moved into the register is usually necessary before the next transfer can be made. See
“REP/REPE/REPZ/REPNE /REPNZ—Repeat String Operation Prefix” on page 4:337
for a
description of the REP prefix.
Operation
IF (byte load)
THEN
AL
SRC; (* byte load *)
THEN IF DF = 0
THEN (E)SI
1;
ELSE (E)SI
-1;
FI;
ELSE IF (word load)
THEN
AX
SRC; (* word load *)
THEN IF DF = 0
THEN SI
2;
ELSE SI
-2;
FI;
ELSE (* doubleword transfer *)
EAX
SRC; (* doubleword load *)
Opcode
Instruction
Description
AC
LODS DS:(E)SI
Load byte at address DS:(E)SI into AL
AD
LODS DS:SI
Load word at address DS:SI into AX
AD
LODS DS:ESI
Load doubleword at address DS:ESI into EAX
AC
LODSB
Load byte at address DS:(E)SI into AL
AD
LODSW
Load word at address DS:SI into AX
AD
LODSD
Load doubleword at address DS:ESI into EAX
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...