Volume 4: Base IA-32 Instruction Reference
4:143
FLDENV—Load FPU Environment
Description
Loads the complete FPU operating environment from memory into the FPU registers.
The source operand specifies the first byte of the operating-environment data in
memory.This data is typically written to the specified memory location by a FSTENV or
FNSTENV instruction.
The FPU operating environment consists of the FPU control word, status word, tag
word, instruction pointer, data pointer, and last opcode. See the
Intel
®
64 and IA-32
Architectures Software Developer’s Manual
for the layout in memory of the loaded
environment, depending on the operating mode of the processor (protected or real)
and the size of the current address attribute (16-bit or 32-bit). In virtual-8086 mode,
the real mode layouts are used.
The FLDENV instruction should be executed in the same operating mode as the
corresponding FSTENV/FNSTENV instruction.
If one or more unmasked exception flags are set in the new FPU status word, a
floating-point exception will be generated upon execution of the next floating-point
instruction (except for the no-wait floating-point instructions. To avoid generating
exceptions when loading a new environment, clear all the exception flags in the FPU
status word that is being loaded.
Operation
FPUControlWord
SRC(FPUControlWord);
FPUStatusWord
SRC(FPUStatusWord);
FPUTagWord
SRC(FPUTagWord);
FPUDataPointer
SRC(FPUDataPointer);
FPUInstructionPointer
SRC(FPUInstructionPointer);
FPULastInstructionOpcode
SRC(FPULastInstructionOpcode);
FPU Flags Affected
The C0, C1, C2, C3 flags are loaded.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Floating-point Exceptions
None; however, if an unmasked exception is loaded in the status word, it is generated
upon execution of the next waiting floating-point instruction.
Opcode
Instruction
Description
D9 /4
FLDENV
m14/28byte
Load FPU environment from
m14byte
or
m28byte.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...