Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 287 / 1898

Volume 2, Part 1: System State and Programming Model 2:39
faulting instruction and IIP points to the first byte of the faulting instruction, or (2) for
faults on the second page, IFA contains the bundle address of the second virtual page
and IIP points to the first byte of the faulting IA-32 instruction.
The IFA also specifies a translation’s virtual address when a translation entry is inserted
into the instruction or data TLB. See
“Interruption Vector Descriptions” on page 2:165
and “Translation Insertion Format” on page 2:53 for usages of the IFA. As shown in
Figure 3-11 , all 64-bits of the IFA must be implemented regardless of the size of the
virtual and physical space supported by the processor model (see “Unimplemented
Address Bits” on page 2:73 ). In some implementations, a mov to IFA instruction may
raise an Unimplemented Data Address fault if an unimplemented virtual address is
used.
3.3.5.5 Interruption TLB Insertion Register (ITIR – CR21)
The ITIR receives default translation information from the referenced virtual region
register on a virtual address translation fault. See
“Interruption Vector Descriptions” on
page 2:165 for the fault conditions that set the ITIR. The ITIR provides additional
virtual address translation parameters on an insertion into the instruction or data TLB.
See
“Translation Instructions” on page 2:60 for ITIR usage information. Figure 3-12
and Table 3-8 define the ITIR fields.
Figure 3-11. Interruption Faulting Address (IFA – CR20)
63 0
IFA
64
Figure 3-12. Interruption TLB Insertion Register (ITIR)
63 32 31 8 7 2 1 0
rv/ci key ps rv/ci
32 24 6 2
Table 3-8. ITIR Fields
Field Bits Description
rv/ci 63:32,
1:0 Reserved / Check on Insert – On a read these fields may return zeros or the value last
written to them. If a non-zero value is written, a Reserved Register/Field fault may be
raised on the mov to ITIR instruction. If not, a subsequent TLB insert will raise a
Reserved Register Field fault depending on other parameters to the insert.
See
“Translation Insertion Format” on page 2:53. On an instruction or data translation fault,
these fields are set to zero.
ps 7:2 Page Size – On a TLB insert, specifies the size of the virtual to physical address
mapping.
If an unsupported page size is written, a Reserved Register/Field fault may be
raised on the mov to ITIR instruction. If not, a subsequent TLB insert will raise a
Reserved Register/Field fault.
See “Translation Insertion Format” on page 2:53. On an
instruction or data translation fault, this field is set to the accessed region’s page size
(RR.ps).
key 31:8 Protection Key – On a TLB insert specifies a protection key that uniquely tags
translations to a protection domain. If non-zero values are written to unimplemented
protection key bits, a Reserved Register/Field fault may be raised on the mov to ITIR
instruction. If not, a subsequent TLB insert will raise a Reserved Register/Field fault
depending on other parameters to the insert.
See “Translation Insertion Format” on
page 2:53. On an instruction or data translation fault, this field is set to the accessed
Region Identifier (RR.rid).