Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 193 / 1898

1:182 Volume 1, Part 2: Software Pipelining and Loop Support
This section describes two general methods for overlapping loop iterations, both of
which result in code expansion on traditional architectures. The code expansion
problem is addressed by loop support features in the Itanium architecture that are
explored later in this chapter. The loop above will be used as a running example in the
next few sections.
5.3.1 Loop Unrolling
Loop unrolling is a technique that seeks to increase the available instruction level
parallelism by making and scheduling multiple copies of the loop body together. The
registers in each copy of the loop body are given different names to avoid unnecessary
WAW and WAR data dependencies. The code below shows the loop from our example
on
page 1:181 after unrolling twice (total of two copies of the original loop body) and
instruction scheduling, assuming two memory ports and a two cycle latency for loads.
For simplicity, assume that the loop trip count is a constant N that is a multiple of two,
so that no exit branch is required after the first copy of the loop body:
L1:
ld4 r4 = [r5],4;; // Cycle 0
ld4 r14 = [r5],4;; // Cycle 1
add r7 = r4,r9;; // Cycle 2
add r17 = r14,r9 // Cycle 3
st4 [r6] = r7,4;; // Cycle 3
st4 [r6] = r17,4 // Cycle 4
br.cloopL1;; // Cycle 4
The above code does not expose as much ILP as possible. The two loads are serialized
because they both use and update
r5
. Similarly the two stores both use and update
r6
.
A variable which is incremented (or decremented) once each iteration by the same
amount is called an induction variable. The single induction variable
r5
(and similarly
r6
) can be expanded into two registers as shown in the code below:
add r15 = 4,r5
add r16 = 4,r6;;
L1: ld4 r4 = [r5],8 // Cycle 0
ld4 r14 = [r15],8;; // Cycle 0
add r7 = r4,r9 // Cycle 2
add r17 = r14,r9;; // Cycle 2
st4 [r6] r7,8 // Cycle 3
st4 [r16] = r17,8 // Cycle 3
br.cloopL1;; // Cycle 3
Compared to the original loop on page 1:181 , twice as many functional units are
utilized and the code size is twice as large. However, no instructions are issued in cycle
1 and the functional units are still under utilized in the remaining cycles. The