Volume 1, Part 2: Software Pipelining and Loop Support
1:181
Software Pipelining and Loop Support
5
5.1
Overview
The Itanium architecture provides extensive support for software-pipelined loops,
including register rotation, special loop branches, and application registers. When
combined with predication and support for speculation, these features help to reduce
code expansion, path length, and branch mispredictions for loops that can be software
pipelined.
The beginning of this chapter reviews basic loop terminology and instructions, and
describes the problems that arise when optimizing loops in the absence of architectural
support. Specific loop support features of the Itanium architecture are then introduced.
The remainder of this chapter describes the programming and optimization of various
type of loops.
5.2
Loop Terminology and Basic Loop Support
Loops can be categorized into two types: counted and while. In counted loops, the loop
condition is based on the value of a loop counter and the trip count can be computed
prior to starting the loop. In while loops, the loop condition is a more general
calculation (not a simple count) and the trip count is unknown. Both types are directly
supported in the architecture.
The Itanium architecture improves the performance of conventional counted loops by
providing a special counted loop branch (the
br.cloop
instruction) and the Loop Count
application register (
LC
). The
br.cloop
instruction does not have a branch predicate.
Instead, the branching decision is based on the value of the
LC
register. If the
LC
register is greater than zero, it is decremented and the
br.cloop
branch is taken.
5.3
Optimization of Loops
In many loops, there are not enough independent instructions within a single iteration
to hide execution latency and make full use of the functional units. For example, in the
loop body below, there is very little ILP:
L1:
ld4
r4 = [r5],4;;
// Cycle 0 load postinc 4
add
r7 = r4,r9;;
// Cycle 2
st4
[r6] = r7,4
// Cycle 3 store postinc 4
br.cloopL1;;
// Cycle 3
In this code, all the instructions from iteration X are executed before iteration X+1 is
started. Assuming that the store from iteration X and the load from iteration X+1 are
independent memory references, utilization of the functional units could be improved
by moving independent instructions from iteration X+1 to iteration X, effectively
overlapping iteration X with iteration X+1.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...