Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 444 / 1898

2:196 Volume 2, Part 1: Interruption Vector Descriptions
Name
NaT Consumption vector (0x5600)
Cause A non-speculative operation (including IA-32) (e.g., load, store, control register access,
instruction fetch etc.) read a NaT source register, NaTVal source register, or referenced
a NaTPage.
Interruptions on this vector:
IR Data NaT Page Consumption fault
Instruction NaT Page Consumption fault
Register NaT Consumption fault
Data NaT Page Consumption fault
Parameters
IIP, IPSR, IIPA, IFS – are defined; refer to page 2:165 for a detailed description.
IIB0, IIB1 – If implemented, for Register NaT Consumption and Data NaT Page
Consumption faults, the IIB registers contain the instruction bundle pointed to by IIP.
The IIB registers are undefined for IR Data NaT Page Consumption and Instruction NaT
Page Consumption faults. Please refer to
Section 3.3.5.10, “Interruption Instruction
Bundle Registers (IIB0-1 – CR26, 27)” on page 2:42 for details on the IIB registers.
If the fault is due to a Data NaT Page Consumption fault or an IR Data NaT Page
Consumption fault:
A non-speculative Itanium integer/FP instruction or instruction fetch or IA-32 data
memory reference accessed a page with the NaTPage memory attribute.
• IFA – faulting data address.
• ISR – The value for the ISR bits depend on the type of access performed and are
specified below. For mandatory RSE fill or spill references, ISR.ed is always 0. For
the IA-32 instruction set, ISR.ed, ei, ni, ir, rs and na bits are 0. For
probe.fault
or
lfetch.fault
the ISR.na bit is set.
If the fault is due to an Instruction NaT Page Consumption fault:
A non-speculative Itanium integer/FP instruction or instruction fetch accessed a
page with the NaTPage memory attribute.
• IFA – The virtual address of the bundle or the 16 byte aligned IA-32 instruction
address zero extended to 64-bits.
• ISR – The value for the ISR bits depend on the type of access performed and are
specified below. For the IA-32 instruction set, ISR.ni and ei bits are 0.
If the fault is due to an Register NaT Consumption fault:
A non-speculative Itanium instruction reads a NaT’ed GR or an FR containing
NaTVal. An IA-32 integer instruction reads a NaT’ed GR. For IA-32 instructions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 2 code{3:0}
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 0 ei so ni ir rs 0 na r w 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 2 0
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0 0 ei 0 ni 0 0 0 0 0 0 1