Volume 1, Part 1: Application Programming Model
1:51
4.2.1
Arithmetic Instructions
Addition and subtraction (
add
,
sub
) are supported with regular two input forms and
special three input forms. The three input addition form adds one to the sum of two
input registers. The three input subtraction form subtracts one from the difference of
two input registers. The three input forms share the same mnemonics as the two input
forms and are specified by appending a “1” as a third source operand.
The immediate form of addition uses a register and a 14-bit immediate; the immediate
form of subtraction uses a register and an 8-bit immediate. In both cases, the
immediate is sign-extended before being added or subtracted. The immediate form is
obtained simply by specifying an immediate rather than a register as the first operand.
Also, addition can be performed between a register and a 22-bit immediate; however,
the source register must be GR 0, 1, 2 or 3.
A shift left and add instruction (
shladd
) shifts one register operand to the left by 1 to 4
bits and adds the result to a second register operand.
32-bit multiplication is supported with the unsigned integer multiply (
mpy4
) instruction,
which takes two 32-bit (unsigned) register operands and produces a 64-bit result. The
unsigned integer shift left and multiply (
mpyshl4
) instruction provides a building block
for doing 64-bit multiplication. It takes a 32-bit operand in the upper half of a first
register, a 32-bit operand in the lower half of a second register, multiplies them, and
places the least significant 32-bits of the product in the upper half of the result register,
with zeros in the lower half.
summarizes the integer arithmetic instructions.
Note that an integer multiply instruction is defined which uses the floating-point
registers. See
“Integer Multiply and Add Instructions” on page 1:101
for details.
Integer divide is performed in software similarly to floating-point divide.
4.2.2
Logical Instructions
Instructions to perform logical AND (
and
), OR (
or
), and exclusive OR (
xor
) between
two registers or between a register and an immediate are defined. The
andcm
instruction performs a logical AND of a register or an immediate with the complement
of another register.
summarizes the integer logical instructions.
Table 4-3.
Integer Arithmetic Instructions
Mnemonic
Operation
add
Addition
add...,1
Three input addition
mpy4
Unsigned integer multiply
mpyshl4
Unsigned integer shift left and multiply
sub
Subtraction
sub...,1
Three input subtraction
shladd
Shift left and add
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...