Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 509 / 1898

Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications 2:261
10.6.2 IA-32 Virtual Memory References
By definition, IA-32 instruction and data memory references are confined to 32-bits of
virtual addressing, the first 4 G-bytes of virtual region 0. However, IA-32 memory
references can be mapped anywhere within the implemented physical address space by
operating system code.
Virtual addresses are converted into physical addresses through the process defined in
Section 4.1, “Virtual Addressing” on page 2:45 . IA-32 references use the Itanium TLB
resources as follows.
• Region Identifiers
–
Operating systems can place IA-32 processes within virtual
region 0, and use the entire 2
24
region identifier name space. By using region
identifiers there is no requirement to flush IA-32 mappings on a context switch.
• Protection Keys
–
Operating systems can place mappings used by IA-32
processes within any number of protection domains. If PSR.pk is 1, all IA-32
references search the Protection Key Registers (PKR) for matching keys. If a key is
not found, a Key Miss fault is generated. Otherwise, key read, write, execute
permissions are verified.
• TLB Access Bit
–
If this bit is zero, an Access Bit fault is generated during Itanium
or IA-32 instruction set memory references. Note: the processor does not
automatically set the Access bit in the VHPT on every reference to the page. Access
bit updates are controlled by the operating system.
• TLB Dirty Bit
–
If this bit is zero, a Dirty bit fault is generated during any Itanium
or IA-32 instruction that stores to a dirty page. Note: the processor does not
automatically set the Dirty bit in the VHPT on every write. Dirty bit updates are
managed by the operating system.
10.6.3 IA-32 TLB Forward Progress Requirements
To ensure forward progress while executing IA-32 instructions, additional TLB resources
and replacement policies must be defined over and above the definition given in
Section 4.1.1.2, “Translation Cache (TC)” on page 2:49 . IA-32 instructions and data
accesses may not be aligned resulting in a worst case scenario for two possible pages
being referenced for every memory datum referenced during the execution of an IA-32
instruction. Furthermore, the worst case non-intercepted IA-32 opcode can reference
up to 4 independent data pages.
The Translation Cache’s (TC) are required to have the following minimum set of
resources to ensure forward progress. Given that software TLB fills can be used to
insert entries into the TLB and a hardware page table walker is not necessarily used,
the following requirements must be satisfied by the processor:
• Instruction Translation Cache
–
at least 1 way set associative with 2 sets, or 2
entries in a fully associative design. Replacement algorithms must not consistently
displace the last 2 entries installed by software.
• Data Translation Cache
–
at least 4 way set associative with 2 sets, or 8 entries in a
fully associative design. Replacement algorithms must not consistently displace the
last 8 entries installed by software or the last 8 translations referenced by an IA-32
instruction.