Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 837 / 1898

Volume 2, Part 2: Floating-point System Software 2:589
the same as what is done when the IEEE Overflow or Underflow exceptions are enabled.
However, hardware implementations will limit the cases that raise SWA Traps for
performance reasons. The most likely case would be for the production of denormalized
results.
For tiny
1
results, the SWA Trap handler has the simpler task of taking the intermediate
result of the first IEEE rounding, the ISR.fpa and ISR.i status bits and producing the
correctly rounded and signed minimum normal, denormal or zero. For huge
2
results,
the SWA Trap handler has the even simpler task of taking the intermediate result of the
first rounding and producing the correctly signed maximum representable normal or
infinity, based on the sign of the result, the rounding direction, and the result precision
and range.
Note: The Itanium architecture also allows for SWA Traps to be raised when the result
is just Inexact. This is a trivial case for the SWA Trap handler, since result of the
second IEEE rounding is identical to the first IEEE rounding.
The general flow of the SWA Trap handler is as follows:
1. From the interruption instruction previous address (IIPA) and exception
instruction index (ISR.ei), determine the FP instruction that trapped.
2. From the instruction, decode the opcode, static precision, status field and
1. Tiny numbers are non-zero values with a magnitude smaller than the smallest normal floating-point
number.
2. Huge numbers have values larger in magnitude than the largest normal floating-point number.
Figure 8-1. Overview of Floating-point Exception Handling in the Intel
®
Itanium
®
Architecture
User Space
User Application
User Exception Handler
IEEE Filter
OS Kernel
Fault/Trap Vector
PAL
Intel
®
Itanium
®
Processor Hardware
IEEE?
"Ease of Use"
"Functionality"
Boot Time
Itanium
®
-based System
000957a
FP SWA
EFI
FP Emulation Library