Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 566 / 1898

2:318 Volume 2, Part 1: Processor Abstraction Layer
parameters. Each P-state maps to a set of values for the domain parameters, and
hence a P-state transition results in a change in the underlying power/performance
characteristics for the logical processor.
The Itanium architecture supports different types of dependency domains, which
enables software to have different degrees of control for P-state changes affecting
logical processors in the domain.
A software-coordinated dependency domain (SCDD) relies on the software to
coordinate P-state changes among the processors in that dependency domain.
Software will have knowledge about logical processors belonging to that domain, and
will decide when it is appropriate to request the P-state transition. The software policy
has to be aware that a P-state change on any logical processor will change the P-state
for all logical processors in that domain. As an example, let us assume that the SCDD
consisted of two cores with the same clock and power distribution networks and the
intent of the software policy was to lower power/performance only when the workload
utilization was low on both cores. Software could then monitor utilization on both cores,
and when both cores were under-utilized (i.e., were running at a higher performance
P-state than required by the current system demand), it could migrate one of the cores
to a lower performance P-state. This transition would simultaneously reduce
performance and power dissipation for both cores, and would result in both cores
operating at the same lower P-state.
A hardware-coordinated dependency domain (HCDD) relies on hardware-based
mechanisms to synchronize P-state changes. Software can make independent P-state
change requests on individual processors, recognizing that hardware is responsible for
the required coordination with other processors in the same HCDD. Hardware-based
coordination mechanisms would be implemented to allow for changes to the logical
processor's power and performance local parameters (which are
implementation-dependant), in addition to the existing domain parameters. Hardware
would use a combination of changes to both of these parameters to satisfy the
software-initiated P-state change request. This type of coordination mechanism is
effective when it is desired to have individual control over all logical processors, and
when the hardware has local parameters for power/performance at the logical
processor level. The local parameters allow for fine-grained control (affecting only the
logical processor power/performance), whereas the domain parameters allow for
coarse-grained control (affecting all logical processors). Domain parameters are set by
hardware according to the highest requested power/performance level (i.e., the lowest
numbered P-state) of the logical processors in the power domain. As an example, let us
assume that the HCDD consisted of two cores with the same clock and power
distribution networks, and that there were also some other techniques to affect power
and performance which were local to each logical processor. Let us also assume that
software has initially set both cores to the P0 state. When software initiates a P-state
transition to P1 (which is a lower power/performance level) on the first core, hardware
would use only the local parameters to carry out the request, and the domain
parameters would remain at P0. Suppose software on the second core then initiates a
P-state transition to P3. Hardware would then set the local parameters for the second
core to reflect this request, undo the changes to the local parameters for the first core
plus initiate changes to the domain parameters to transition the domain to the P1 state
(the highest requested power/performance level of the two cores).