Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 766 / 1898

2:518 Volume 2, Part 2: MP Coherence and Synchronization
2.2.1.8 Store Buffers May Satisfy Local Loads
In the Itanium memory ordering model, store buffers (or other logically-equivalent
structures) may satisfy local read requests from loads or acquire loads even if the
stored data is not yet visible to other agents in the coherence domain. Such bypassing
must honor any ordering semantics in the memory reference stream.
Table 2-10 and
Table 2-11 that Section 2.2.1.9 presents illustrate this behavior.
.
In this sequence, each processor bypasses its locally-written value from a store buffer
before the value becomes visible to the other processor. This behavior may make
accesses of different sizes that have overlapping memory addresses appear to complete
non-atomically.
The following discussion focuses on the outcome r1 = 1, r3 = 1, r2 = 0, and r4 = 0
because this outcome is allowed if and only if store buffers can satisfy local loads (other
outcomes are allowed but do not depend on being able to satisfy local loads from a
store buffer).
The Itanium memory ordering semantics only require that and .
There are no constraints on the relative ordering of M1 and M2 or M3 nor on the relative
ordering of M4 and M5 or M6.
Remember that both dependencies and the memory ordering model place requirements
on the manner in which a processor based on the Itanium architecture may re-order
accesses. Even though the Itanium memory ordering model allows loads to pass stores,
a processor based on the Itanium architecture cannot re-order the following sequence:
st.rel [x] = r0 // M1: store 0 to [x]
ld.acq r1 = [x] // M2: cannot move above st.rel due to RAW
This is because there is a RAW dependency through memory between M1 and M2 and
the Itanium memory ordering model requires that the local processor resolve RAW,
WAR, and WAW dependencies between its memory accesses in program order. Thus,
even though the ordering semantics place no constraints on the relative
ordering of M1 and M2.
Because there is a RAW dependency through memory between M1 and M2 and between
M4 and M5, the ordering constraints
effectively become:
1
Table 2-10. Store Buffers May Satisfy Loads if the Stored Data is Not Yet
Globally Visible
Processor #0 Processor #1
st.rel [x] = 1 // M1
ld.acq r1 = [x] // M2
ld r2 = [y] // M3
st.rel [y] = 1 // M4
ld.acq r3 = [y] // M5
ld r4 = [x] // M6
Outcome: r1 = 1, r3 = 1, r2 = 0, and r4 = 0 is allowed
1. That is, the store operations must become visible to the local processors before their loads that read
the stored value.
M2 M3

M5 M6

M1 M2

M1 M2 M3
 
M4 M5 M6
 