2:322
Volume 2, Part 1: Processor Abstraction Layer
As seen above, for a HCDD, the PAL_GET_PSTATE procedure allows the caller to get
feedback on the dynamic performance of the processor over a software-controlled time
period. The caller can use this information to get better system utilization over a
subsequent time period by changing the P-state in correlation with the current
workload demand. The caller can also use PAL_GET_PSTATE to see the most recent
P-state set for this logical processor (
type
=0) and the instantaneous current P-state
that the domain parameters are set to (
type
=3). Platform power-caps do not affect
either of these return values.
HIDD: If the logical processor belongs to a hardware-independent dependency domain,
a weighted-average performance index can be returned by PAL_GET_PSTATE (
type
=1
or 2). Since software could calculate the performance index based on P-states it set,
the weighted-average performance index is only of value when factoring in the effect of
platform power-caps.
Note that P-state transitions typically do not happen instantaneously. An
implementation-specific amount of time is required for a given transition to complete.
The computation of the weighted-average
performance_index
may not take into
account the fact that transitions of power/performance are gradual, but may be done as
though they were instantaneous at the point when the transition starts. The
expectation is that any errors in computing the
performance_index
due to
non-instantaneous transitions to higher and lower P-states will tend to cancel out, and
to the extent that they do not, will be insignificant.
11.6.1.4
Variable P-state Performance
Some processors support variable P-state performance which allows the frequency to
vary within a given P-state in order to achieve the maximum performance for that
P-state's power budget. The PAL_PROC_GET_FEATURES procedure indicates whether
the processor supports variable P-state performance (see
– Get Processor Dependent Features (17)” on page 2:446
for details).
Since the frequency within a P-state can vary, the performance index calculation is
slightly different when a processor supports variable P-state performance. Frequencies
for a given P-state are represented by an index value
F
x,y
. The value
x
is the P-state
number and
y
represents a frequency point in the range from 0 to N. A value of 0
represents the minimum frequency index value for the given P-state. For example:
F
0,0
to
F
0,N
– Frequency index values for the P0 state
F
1,0
to
F
1,N
– Frequency index values for the P1 state
…etc.
F
0,0
is the minimum frequency index for the P0 state and its value is 100.
F
0,1
represents a higher frequency point for P0 and will have a value greater than 100. For
example, if
F
0,1
frequency is 5% greater than
F
0,0
it would have a value of 105.
The
performance_index
equation for P0 is calculated as follows:
((
F
0,0
* time spent in
F
0,0
) + (
F
0,1
* time spent in
F
0,1
)+ .. (
F
0,N
* time spent in
F
0,N
)) /
(Total Time spent in
P
0
)
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...