Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 410 / 1898

2:162 Volume 2, Part 1: Debugging and Performance Monitoring
Multiple overflow bits may be set to 1, if counters overflow concurrently. The overflow
bits and the freeze bit are sticky; i.e., the processor sets them to 1 but never resets
them to 0. It is software's responsibility to reset the overflow and freeze bits.
The overflow status bits are populated only for implemented counters. Overflow bits of
unimplemented counters read as zero and writes are ignored.
7.2.3 Performance Monitor Events
The set of monitored events is implementation-specific. All processor models are
required to provide at least two events:
1. The number of retired instructions. These are defined as all instructions which
execute without a fault, including nops and those which were predicated off.
Generic counters configured for this event count only when the processor is in the
NORMAL or LOW-POWER state (see
Figure 11-8 on page 2:314 ).
2. The number of processor clock cycles. Generic counters configured for this event
count only when the processor is in the NORMAL or LOW-POWER state (see
Figure 11-8 on page 2:314 ).
Events may be monitorable only by a subset of the available counters. PAL calls provide
an implementation-independent interface that provides information on the number of
implemented counters, their bit-width, the number and location of other (non-counter)
monitors, etc.
7.2.4 Implementation-independent Performance Monitor Code
Sequences
This section describes implementation-independent code sequences for servicing
overflow interrupts and context switches of the performance monitors. For forward
compatibility, the code sequences outlined in
Section 7.2.4.1 and Section 7.2.4.2 use
PAL-provided implementation-specific information to collect/preserve data values for all
implemented counters.
7.2.4.1 Performance Monitor Interrupt Service Routine
When a generic performance counter pair (PMC[n]/PMD[n]) overflows and its overflow
interrupt bit (PMC[n].oi) is 1, or an implementation-dependent monitor wants to report
an event with an interruption, then the processor:
• Sets the corresponding overflow status bit in PMC[0]..PMC[3] to one,
• Raises a Performance Monitor Interrupt, and
• Sets the freeze bit in PMC[0] which suspends event monitoring.
Event monitoring remains frozen until software clears the freeze bit. When the freeze
bit is in-flight, whether counters count events and reads return non-decreasing values
is implementation dependent. Instruction serialization is required to ensure that the
behavior specified by PMC[0].fr is observed. Performance monitor interrupts may be
caused by an overflow of any of the counters. The processor indicates which
performance monitor overflowed in the performance monitor overflow status registers
(PMC[0]...PMC[3]). If multiple counters overflow concurrently, multiple overflow bits
will be set to one. For forward compatibility, event collection interrupt handlers must