Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 483 / 1898

Volume 2, Part 1: IA-32 Interruption Vector Descriptions 2:235
Name
IA_32_Intercept (Gate) – Gate Intercept Trap
Cause If an IA-32 control transfer is initiated through a GDT/LDT descriptor that transfers
control through a Call Gate, Task Gate or Task Segment this interception trap is
generated.
Parameters
IIPA – trapping virtual IA-32 instruction address zero extended to 64-bits.
IIP – next sequential virtual IA-32 instruction address zero extended to 64-bits.
IFA – Gate Selector. The gate selector is loaded in IFA{15:0}.
IIM – Gate, Task Gate or Task Segment Descriptor. The descriptor loaded in IIM adheres
to the IA-32 GDT/LDT memory format, where byte 0 of the descriptor is in IIM{7:0}.
ISR.vector – 1, indicates gate interception.
ISR.code – TrapCode, Indicates Concurrent Data Debug, taken Branch, and Single Step
Events.
ISR.code{15:14} – indicates whether CALL or JMP generated the trap. See Table 9-3
for details.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved gate selector
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
gate_descriptor{31:0}
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
gate_descriptor{63:32}
Table 9-3. Gate Intercept Trap Code Identifier
Instruction ISR.code{15:14}
CALL 00
JMP 01
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rv 1 ident trap_code
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
rv 0 0 0 0 0 0 0 0 0 0 0