Volume 1, Part 1: Application Programming Model
1:61
indicates that the register contains a deferred exception token, and that its 64-bit data
portion contains an implementation-specific value that software cannot rely upon. In
floating-point registers, a deferred exception is indicated by a specific pseudo-zero
encoding called the NaTVal (see
“Representation of Values in Floating-point Registers”
for details).
4.4.4.2
Control Speculation and Instructions
Instructions are divided into two categories: speculative (instructions which can be
used speculatively) and non-speculative (instructions which cannot). Non-speculative
instructions will raise exceptions if they occur and are therefore unsafe to schedule
before they are known to be executed. Speculative instructions defer exceptions (they
do not raise them) and are therefore safe to schedule before they are know to be
executed.
Loads to general and floating-point registers have both non-speculative (
ld
,
ldf
,
ldfp
)
and speculative (
ld.s
,
ldf.s
,
ldfp.s
) variants. Generally, all computation instructions
which write their results to general or floating-point registers are speculative. Any
instruction that modifies state other than a general or floating-point register is
non-speculative, since there would be no way to represent the deferred exception
(there are a few exceptions).
Deferred exception tokens propagate through the program in a dataflow manner. A
speculative instruction that reads a register containing a deferred exception token will
propagate a deferred exception token into its target. Thus a chain of instructions can be
executed speculatively, and only the result register need be checked for a deferred
exception token to determine whether any exceptions occurred.
At the point in the program when it is known that the result of a speculative calculation
is needed, a speculation check (
chk.s
) instruction is used. This instruction tests for a
deferred exception token. If none is found, then the speculative calculation was
successful, and execution continues normally. If a deferred exception token is found,
then the speculative calculation was unsuccessful and must be re-done. In this case,
the
chk.s
instruction branches to a new address (specified by an immediate offset in
the
chk.s
instruction). Software can use this mechanism to invoke code that contains a
copy of the speculative calculation (but with non-speculative loads). Since it is now
known that the calculation is required, any exceptions which now occur can be signalled
and handled normally.
Since computational instructions do not generally cause exceptions, the only
instructions which generate deferred exception tokens are speculative loads. (IEEE
floating-point exceptions are handled specially through a set of alternate status fields.
See
“Floating-point Status Register” on page 1:88
.) Other speculative instructions
propagate deferred exception tokens, but do not generate them.
4.4.4.3
Control Speculation and Compares
As stated earlier, most instructions that write a register file other than the general
registers or the floating-point registers are non-speculative. The compare (
cmp
,
cmp4
,
fcmp
), test bit (
tbit
), floating-point class (
fclass
), and floating-point approximation
(
frcpa
,
frsqrta
) instructions are special cases. These instructions read general or
floating-point registers and write one or two predicate registers.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...