Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1608 / 1898

4:306 Volume 4: Base IA-32 Instruction Reference
OUT—Output to Port
Description
Copies the value from the second operand (source operand) to the I/O port specified
with the destination operand (first operand). The source operand can be register AL,
AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits,
respectively); the destination operand can be a byte-immediate or the DX register.
Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the
DX register as a source operand allows I/O ports from 0 to 65,535 to be accessed.
When accessing an 8-bit I/O port, the opcode determines the port size; when accessing
a 16- and 32-bit I/O port, the operand-size attribute determines the port size.
At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports.
Here, the upper eight bits of the port address will be 0.
This instruction is only useful for accessing I/O ports located in the processor’s I/O
address space.
I/O transactions are performed after all prior data memory operations. No
subsequent data memory operations can pass an I/O transaction.
In the Itanium System Environment, I/O port references are mapped into the
64-bit virtual address pointed to by the IOBase register, with four ports per
4K-byte virtual page. Operating systems can utilize TLBs in the Itanium
architecture to grant or deny permission to any four I/O ports. The I/O port
space can be mapped into any arbitrary 64-bit physical memory location by
operating system code. If CFLG.io is 1 and CPL>IOPL, the TSS is consulted for
I/O permission. If CFLG.io is 0 or CPL<=IOPL, permission is granted
regardless of the state of the TSS I/O permission bitmap (the bitmap is not
referenced).
If the referenced I/O port is mapped to an unimplemented virtual address (via
the I/O Base register) or if data translations are disabled (PSR.dt is 0) a
GPFault is generated on the referencing OUT instruction.
Operation
IF ((PE = 1) AND ((VM = 1) OR (CPL > IOPL)))
THEN (* Protected mode or virtual-8086 mode with CPL > IOPL *)
IF ( CFLG.io AND Any I/O Permission Bit for I/O port being accessed = 1)
THEN #GP(0);
FI;
ELSE ( * Real-address mode or protected mode with CPL

IOPL *)
Opcode Instruction Description
E6 ib OUT imm8 , AL Output byte AL to imm8 I/O port address
E7 ib OUT imm8 , AX Output word AX to imm8 I/O port address
E7 ib OUT imm8 , EAX Output doubleword EAX to imm8 I/O port address
EE OUT DX, AL Output byte AL to I/O port address in DX
EF OUT DX, AX Output word AX to I/O port address in DX
EF OUT DX, EAX Output doubleword EAX to I/O port address in DX