Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1380 / 1898

4:78 Volume 4: Base IA-32 Instruction Reference
CPUID—CPU Identification
Description
Returns processor identification and feature information in the EAX, EBX, ECX, and EDX
registers. The information returned is selected by entering a value in the EAX register
before the instruction is executed.
Table 2-4 shows the information returned,
depending on the initial value loaded into the EAX register.
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction.
If a software procedure can set and clear this flag, the processor executing the
procedure supports the CPUID instruction.
The information returned with the CPUID instruction is divided into two groups: basic
information and extended function information. Basic information is returned by
entering an input value starting at 0 in the EAX register; extended function information
is returned by entering an input value starting at 80000000H. When the input value in
the EAX register is 0, the processor returns the highest value the CPUID instruction
recognizes in the EAX register for returning basic information. Always use an EAX
parameter value that is equal to or greater than zero and less than or equal to this
highest EAX return value for basic information. When the input value in the EAX
register is 80000000H, the processor returns the highest value the CPUID instruction
recognizes in the EAX register for returning extended function information. Always use
an EAX parameter value that is equal to or greater than zero and less than or equal to
this highest EAX return value for extended function information.
The CPUID instruction can be executed at any privilege level to serialize instruction
execution. Serializing instruction execution guarantees that any modifications to flags,
registers, and memory for previous instructions are completed before the next
instruction is fetched and executed.
Opcode Instruction Description
0F A2 CPUID Returns processor identification and feature information in the
EAX, EBX, ECX, and EDX registers, according to the input
value entered initially in the EAX register.
Table 2-4. Information Returned by CPUID Instruction
Initial EAX Value Information Provided about the Processor
Basic CPUID Information
0 EAX
EBX
ECX
EDX Maximum CPUID Input Value
756E6547H “Genu” (G in BL)
6C65746EH “ntel” (n in CL)
49656E69H “ineI” (i in DL)
1H EAX
EBX
ECX
EDX
Version Information (Type, Family, Model, and Stepping ID)
Bits 7-0:
Brand Index
a
Bits 15-8: CLFLUSH line size (Value * 8 = cache line size in bytes)
Bits 23-16: Number of logical processors per physical processor
Bits 31-24: Local APIC ID
b
Reserved
Feature Information (see
Table 2-5 )
2H EAX
EBX
ECX
EDX Cache and TLB Information
Cache and TLB Information
Cache and TLB Information
Cache and TLB Information