3:210
Volume 3: Instruction Reference
pmax
Operation:
if (PR[
qp
]) {
check_target_register(
r
1
);
if (one_byte_form) {
// one-byte elements
x[0] = GR[
r
2
]{7:0}; y[0]
=
GR[
r
3
]{7:0};
x[1] = GR[
r
2
]{15:8};
y[1] = GR[
r
3
]{15:8};
x[2] = GR[
r
2
]{23:16};
y[2] = GR[
r
3
]{23:16};
x[3] = GR[
r
2
]{31:24};
y[3] = GR[
r
3
]{31:24};
x[4] = GR[
r
2
]{39:32};
y[4] = GR[
r
3
]{39:32};
x[5] = GR[
r
2
]{47:40};
y[5] = GR[
r
3
]{47:40};
x[6] = GR[
r
2
]{55:48};
y[6] = GR[
r
3
]{55:48};
x[7] = GR[
r
2
]{63:56};
y[7] = GR[
r
3
]{63:56};
for (i = 0; i < 8; i++) {
res[i] = (zero_ext(x[i],8) < zero_ext(y[i],8)) ? y[i] : x[i];
}
GR[
r
1
] = concatenate8(res[7], res[6], res[5], res[4],
res[3], res[2], res[1], res[0]);
} else {
// two-byte elements
x[0] = GR[
r
2
]{15:0};
y[0] = GR[
r
3
]{15:0};
x[1] = GR[
r
2
]{31:16};
y[1] = GR[
r
3
]{31:16};
x[2] = GR[
r
2
]{47:32};
y[2] = GR[
r
3
]{47:32};
x[3] = GR[
r
2
]{63:48};
y[3] = GR[
r
3
]{63:48};
for (i = 0; i < 4; i++) {
res[i] = (sign_ext(x[i],16) < sign_ext(y[i],16)) ? y[i] : x[i];
}
GR[
r
1
] = concatenate4(res[3], res[2], res[1], res[0]);
}
GR[
r
1
].nat = GR[
r
2
].nat || GR[
r
3
].nat;
}
Interruptions:
Illegal Operation fault
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...