Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1161 / 1898

3:262 Volume 3: Instruction Reference
tbit
Operation: if (PR[qp]) {
if ( p
1
== p
2
)
illegal_operation_fault();
if ( trel == ‘nz’) // ‘nz’ - test for 1
tmp_rel = GR[ r
3
]{ pos
6
};
else // ‘z’ - test for 0
tmp_rel = !GR[ r
3
]{ pos
6
};
switch ( ctype ) {
case ‘and’: // and-type compare
if (GR[ r
3
].nat || !tmp_rel) {
PR[ p
1
] = 0;
PR[ p
2
] = 0;
}
break;
case ‘or’: // or-type compare
if (!GR[ r
3
].nat && tmp_rel) {
PR[ p
1
] = 1;
PR[ p
2
] = 1;
}
break;
case ‘or.andcm’: // or.andcm-type compare
if (!GR[ r
3
].nat && tmp_rel) {
PR[ p
1
] = 1;
PR[ p
2
] = 0;
}
break;
case ‘unc’: // unc-type compare
default: // normal compare
if (GR[ r
3
].nat) {
PR[ p
1
] = 0;
PR[ p
2
] = 0;
} else {
PR[ p
1
] = tmp_rel;
PR[ p
2
] = !tmp_rel;
}
break;
}
} else {
if ( ctype == ‘unc’) {
if ( p
1
== p
2
)
illegal_operation_fault();
PR[ p
1
] = 0;
PR[ p
2
] = 0;
}
}
Interruptions:
Illegal Operation fault