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Volume 2, Part 2: Memory Management
5.1.2
Protection Keys
The Itanium architecture provides two mechanisms for applying protection to pages.
The first mechanism is the access rights bits associated with each translation. These
bits provide privilege level-granular access to a page. The second mechanism is the
protection keys. Protection keys permit domain-granular access to a page. These are
especially useful for mapping shared code and data segments in a globally shared
region, and for implementing domains in a single address space (SAS) operating
system.
Protection key checking is enabled via the PSR.pk bit. When PSR.pk is 1, instruction,
data, and RSE references go through protection key access checks during the
virtual-to-physical address translation process.
All processors based on the Itanium architecture implement at least 16 protection key
registers (PKRs) in a protection key register cache. The OS is responsible for
maintaining this cache and keeping track of which protection keys are present in the
cache at any given time.
Each protection key register contains the following fields:
• v – valid bit. When 1, this register contains a valid key, and is checked during
address translation whenever protection keys are enabled (PSR.pk is 1).
• wd – write disable. When 1, write permission is denied to translations which match
this protection key, even if the data TLB access rights permit the write.
• rd – read disable. When 1, read permission is denied to translations which match
this protection key, even if the data TLB access rights permit the read.
• xd – execute disable. When 1, execute permission is denied to translations which
match this protection key, even if the instruction TLB access rights give execute
permission.
• key – protection key. An 18- to 24-bit (depending on the processor
implementation) unique key which tags a translation to a particular protection
domain.
When protection key checking is enabled, the protection key tagged to a referenced
translation is checked against all protection keys found in the protection key register
cache. If a match is found, the protection rights specified by that key are applied to the
translation. If the access being performed is allowed by the matching key, the access
succeeds. If the access being performed is not allowed by the matching key (e.g.
instruction fetch to a translation tagged with a key marked ‘xd’), a Protection Key
Permission fault is raised by the processor. The OS may then decide whether to
terminate the offending program or grant it the requested access.
If no match is found, a Protection Key Miss fault is raised by the processor, and the OS
must insert the correct protection key into the PKRs and retry the access.
Protection keys can be used to provide different access rights to shared translations to
each process. For example, assume a shared data page is tagged with a protection key
number of 0xA. Two processes share this data page: one is the producer of the data on
this page, and the other is only a consumer. When the producer process is running, the
OS will insert a valid PKR with the protection key 0xA and the ‘wd’ and ‘rd’ bits cleared,
to allow this process to both read and write this page. When the consumer process is
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...