Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1740 / 1898

4:438 Volume 4: IA-32 Intel
®
MMX™ Technology Instruction Reference
PSLLW/PSLLD/PSLLQ—Packed Shift Left Logical (continued)
Operation
IF instruction is PSLLW
THEN
DEST(15..0)

DEST(15..0) << COUNT;
DEST(31..16)

DEST(31..16) << COUNT;
DEST(47..32)

DEST(47..32) << COUNT;
DEST(63..48)

DEST(63..48) << COUNT;
ELSE IF instruction is PSLLD
THEN {
DEST(31..0)

DEST(31..0) << COUNT;
DEST(63..32)

DEST(63..32) << COUNT;
ELSE (* instruction is PSLLQ *)
DEST

DEST << COUNT;
FI;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS
or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS segment
limit.
#UD If EM in CR0 is set.
#NM If TS in CR0 is set.
#MF If there is a pending FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real-Address Mode Exceptions
#GP If any part of the operand lies outside of the effective address space
from 0 to FFFFH.
#UD If EM in CR0 is set.
#NM If TS in CR0 is set.
#MF If there is a pending FPU exception.