Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 45 / 1898

1:34 Volume 1, Part 1: Execution Environment
3.1.11 Processor Identification Registers
Application level processor identification information is available in a register file
termed: CPUID. This register file is divided into a fixed region, registers 0 to 4, and a
variable region, register 5 and above. The CPUID[3].number field indicates the
maximum number of 8-byte registers containing processor specific information.
The CPUID registers are unprivileged and accessed using the indirect
mov
(from)
instruction. All registers beyond register CPUID[3].number are reserved and raise a
Reserved Register/Field fault if they are accessed. Writes are not permitted and no
instruction exists for such an operation.
Vendor information is located in CPUID registers 0 and 1 and specify a vendor name, in
ASCII, for the processor implementation (
Figure 3-10 ). All bytes after the end of the
string up to the 16th byte are zero. Earlier ASCII characters are placed in lower number
register and lower numbered byte positions.
CPUID register 2 is an ignored register (reads from this register return zero).
CPUID register 3 contains several fields indicating version information related to the
processor implementation.
Figure 3-11 and Table 3-7 specify the definitions of each
field.
up 2 User performance monitor enable (including IA-32)
0: user performance monitors are disabled
1: user performance monitors are enabled
ac 3 Alignment check for data memory references (including IA-32)
0: unaligned data memory references may cause an Unaligned Data Reference fault.
1: all unaligned data memory references cause an Unaligned Data Reference fault.
mfl 4 Lower (f2.. f31) floating-point registers written – This bit is set to one when an Intel
®
Itanium
®
instruction that uses register f2..f31 as a target register, completes. This bit is
sticky and is only cleared by an explicit write of the user mask. See Section 3.3.2,
“Processor Status Register (PSR)” for conditions when IA-32 instructions set this bit.
mfh 5 Upper (f32.. f127) floating-point registers written – This bit is set to one when an Intel
®
Itanium
®
instruction that uses register f32..f127 as a target register, completes. This bit
is sticky and only cleared by an explicit write of the user mask. See Section 3.3.2,
“Processor Status Register (PSR)” for conditions when IA-32 instructions set this bit.
Figure 3-10. CPUID Registers 0 and 1 – Vendor Information
63 0
CPUID[0] byte 0
CPUID[1] byte 15
64
Figure 3-11. CPUID Register 3 – Version Information
63 40 39 32 31 24 23 16 15 8 7 0
rv archrev family model revision number
24 8 8 8 8 8
Table 3-6. User Mask Field Descriptions (Continued)
Field Bit Description