Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 857 / 1898

Volume 2, Part 2: External Interrupt Architecture 2:609
10.5.3 EOI Usage Example
This example is a typical return from an interrupt service routine to the generic
interrupt handler. Interrupts are disabled before returning to the main trap handler in
preparation for returning from kernel space.
return_from_interrupt:
// disable interrupts here
rsm 0x4000 // make sure interrupts disabled
// interrupt_eoi# clear the sapic/pic interrupt
sapic_eoi:
mov cr.eoi=r0 // issue and eoi
;;
srlz.d // make sure it takes effect
// issue the appropriate EOI sequence to the external interrupt
// controller here.
For level trigger interrupts, the OS is required to issue an EOI not only to the processor,
but also the external interrupt controller where the interrupt originated. This forces the
OS to keep track of whether the vector is associated with a level or an edge trigger
interrupt line.
10.5.4 IRR Usage Example
Waiting on an interrupt with interrupts disabled.
my_interrupt_loop::
//
// check for vector 192 (0xc0) via irr3
//
mov r3=cr.irr3
;;
and r3=0x1,r3
;;
cmp.eq p6,p7=0x1,r3
(p7)br.cond.sptk.few my_interrupt_loop
;;
mov r4=cr.ivr // read the vector
;;
mov cr.eoi=r0 // clear it
;;
10.5.5 Interval Timer Usage Example
The Itanium architecture provides a 64 bit interval timer for elapsed time notification
interrupts. It is similar to the IA-32 Time Stamp Counter (TSC). Programming the
Itanium interval timer consists of initializing the ITV (CR 72), ITM (CR 1), and ITC (AR
44).
The Interval Timer Vector (ITV) specifies the external interrupt vector number for the
Interval Timer Interrupts. The code examples below show how to clear and initialize the
timers vector, match register, and count registers.