Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 834 / 1898

2:586 Volume 2, Part 2: Instruction Emulation and Other Fault Handlers
specified in the
brl.call
instruction with the IP of the successor of the
brl.call
(predication helps here as the Itanium instruction set does not provide an indirect
move to branch register instruction).
• The handler forms the 60-bit immediate IP-offset for the
brl
target from the
i
and
imm20
fields from the X syllable of the bundle (the
brl
instruction) and the
imm39
field from the L syllable of the bundle.
• The handler checks to see if there are any traps to be taken. Specifically, it verifies
that the next IP is at an implemented address (the specific test depends on whether
the processor was in virtual or physical mode at the time of the fault as IPSR.it
indicates), that taken branch traps are not enabled if the branch is taken, and that
single stepping is not enabled.
• If a trap condition is detected, the ISR.code and ISR.vector fields are set up as
appropriate and the handler jumps to the appropriate operating system entry point
after restoring the predicates at the time of the fault and setting the IIP to the
appropriate address.
• If no trap occurs, the handler restores the predicates and returns to the faulting
code at the appropriate IP.
A processor based on the Itanium architecture typically does not fault on instructions
with false qualifying predicates. However, an implementation may take an Illegal
Operation Fault on an MLX instruction with a false predicate; the Itanium processor is
such an implementation. This implies that the
brl
emulation handler must also provide
the means to skip the faulting instruction when its qualifying predicate is false.
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