Volume 1, Part 1: Floating-point Programming Model
1:101
with the FPSR.sf0.flags and FPSR.traps. If the flags of the alternate status field indicate
the occurrence of an event that corresponds to an enabled floating-point exception in
FPSR.traps, or an event that is not already registered in the FPSR.sf0.flags (i.e., the
flag for that event in FPSR.sf0.flags is clear), then the
fchkf
instruction branches to
recovery code. If neither of these cases arise then the
fchkf
instruction does nothing.
The
fsetc
instruction allows bit-wise modification of a status field’s control bits. The
FPSR.sf0.controls are ANDed with a 7-bit immediate and-mask and ORed with a 7-bit
immediate or-mask to produce the control bits for the status field. The
fclrf
instruction clears all of the status field’s flags to zero.
5.3.6
Integer Multiply and Add Instructions
Integer (fixed-point) multiply is executed in the floating-point unit using the
three-operand
xma
instructions. The operands and result of these instructions are
floating-point registers. The
xma
instructions ignore the sign and exponent fields of the
floating-point register, except for a NaTVal check. The product of two 64-bit source
significands is added to the third 64-bit significand (zero extended) to produce a
128-bit result. The low and high versions of the instruction select the appropriate
low/high 64-bits of the 128-bit result, respectively, and write it into the destination
register as a canonical integer. The signed and unsigned versions of the instructions
treat the input multiplicands as signed and unsigned 64-bit integers respectively.
5.4
Additional IEEE Considerations
This section describes the support of the IEEE standard in the areas where specific
details are left open to implementation.
5.4.1
Floating-point Interruptions
Floating-point interruptions are precise. The exception reporting and handling occurs on
the instruction which causes the interruption. There are three floating-point
interruptions: Disabled Floating-Point Register fault, Floating-Point Exception fault, and
Floating-Point Exception trap (see
Chapter 5, “Interruptions” in Volume 2
for more
details).
Table 5-16.
FPSR Status Field Instructions
Operation
Mnemonic(s)
Floating-point check flags
fchkf.
sf
Floating-point clear flags
fclrf.
sf
Floating-point set controls
fsetc.
sf
Table 5-17.
Integer Multiply and Add Instructions
Integer Multiply and Add
Low
High
Signed
xma.l
xma.h
Unsigned
xma.lu (pseudo-op)
xma.hu
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...