Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 328 / 1898

2:80 Volume 2, Part 1: Addressing and Protection
Prefetches are enabled if a speculative translation exists. Prefetches are asynchronous
data and instruction memory accesses that appear logically to initiate and finish
between some pair of instructions. This access may not be visible to subsequent flush
cache (
fc
,
fc.i
) and/or TLB purge instructions. This behavior is
implementation-dependent.
The processor will not initiate memory references (16-byte instruction bundle fetches,
IA-32 instruction fetches, RSE fills and spills, VHPT references, and data memory
accesses) to non-speculative pages until all previous control dependencies (predicates,
branches, and exceptions) are resolved; i.e., the memory reference is required by an
in-order execution of the program. Additionally, for references to non-speculative
pages, the processor:
• May not generate any memory access for a control or data speculative data
reference.
• Will generate exactly one memory access for each aligned, non-speculative data
reference. (Misaligned data references may cause multiple memory accesses,
although these accesses are guaranteed to be non-overlapping – each byte will be
accessed exactly once.)
• May generate multiple 16-byte memory accesses (to the same address) for each
16-byte instruction bundle fetch reference.
To ensure virtual and physical accesses to non-speculative pages are performed in
program order and only once per program order occurrence, the rules in
Table 4-13 and
Table 4-14 are defined. Software should also ensure that RSE spill/fill transactions are
not performed to non-speculative memory that may contain I/O devices; otherwise,
system behavior is undefined.
Table 4-13. Permitted Speculation
Memory
Attribute
Load
(ld)
a
a. Includes the faulting form of line prefetch (
lfetch.fault
).
Speculative
Load
(ld.s)
b
b. Includes the non-faulting form of line prefetch (
lfetch
), which does not cause a cache fill if the memory
attribute is non-speculative or limited speculation.
Advanced
Load
(ld.a)
Speculative
Advanced
Load (ld.sa)
Hardware-generated
Speculative
References
c
c. Hardware-generated speculative references include non-demand instruction prefetches (including IA-32),
hardware-generated data prefetch references, and eager RSE memory references.
Speculative Yes Yes Yes Yes Yes
Non-speculative Yes Always Fail Always Fail Always Fail Prohibited
Limited Speculation Yes Always Fail Yes Always Fail Limited
d
d. The processor may only issue hardware-generated speculative references to a 4K-byte physical page if it is a
verified page.
Table 4-14. Register Return Values on Non-faulting Advanced/Speculative
Loads
Memory
Attribute
Speculative Load
(ld.s)
Advanced Load
(ld.a)
Speculative Advanced Load
(ld.sa)
Success Failure Success Failure Success Failure
Speculative Value Nat
a
Value N/a Value NaT
a
Non-speculative N/A Nat
b
N/A Zero
c
N/A NaT
b
Limited Speculation N/A Nat
b
Value N/a N/a NaT
b